[PATCH] D68742: AMDGPU: Use SGPR_128 instead of SReg_128 for vregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, qcolombet.

SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds
the additional non-allocatable TTMP registers. There's no point in
allocating SReg_128 vregs. This shrinks the size of the classes
regalloc needs to consider, which is usually good.


https://reviews.llvm.org/D68742

Files:
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.td
  test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
  test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
  test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
  test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
  test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
  test/CodeGen/AMDGPU/coalescer-subreg-join.mir
  test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
  test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
  test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
  test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
  test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
  test/CodeGen/AMDGPU/detect-dead-lanes.mir
  test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  test/CodeGen/AMDGPU/fold-imm-copy.mir
  test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
  test/CodeGen/AMDGPU/fold-multiple.mir
  test/CodeGen/AMDGPU/global-load-store-atomics.mir
  test/CodeGen/AMDGPU/memory_clause.mir
  test/CodeGen/AMDGPU/merge-load-store.mir
  test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
  test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
  test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
  test/CodeGen/AMDGPU/regbank-reassign.mir
  test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
  test/CodeGen/AMDGPU/regcoal-subrange-join.mir
  test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
  test/CodeGen/AMDGPU/rename-independent-subregs.mir
  test/CodeGen/AMDGPU/schedule-regpressure.mir
  test/CodeGen/AMDGPU/spill-before-exec.mir
  test/CodeGen/AMDGPU/splitkit.mir
  test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
  test/CodeGen/AMDGPU/subreg_interference.mir
  test/CodeGen/AMDGPU/subvector-test.mir

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