[PATCH] D68360: PR41162 Implement LKK remainder and divisibility algorithms [urem]

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4922
+  // Check to see if we can do this.
+  if (!isTypeLegal(VT) || !isTypeLegal(FVT))
+    return SDValue();
----------------
TG908 wrote:
> This right here seems to fail on riscv64 +m with:
> 
> 
> ```
> (lldb) p FVT
> 
> (llvm::EVT) $1 = {
>   V = (SimpleTy = i64)
>   LLVMTy = 0x0000000000000000
> }
> ```
> ```
> (lldb) p VT
> 
> (llvm::EVT) $2 = {
>   V = (SimpleTy = i32)
>   LLVMTy = 0x0000000000000000
> }
> ```
> Those types should be legal right? What am I missing?
> 
> 
> ```
> (lldb) expr isTypeLegal(VT)
> (bool) $5 = false
> (lldb) expr isTypeLegal(FVT)
> (bool) $6 = true
> ```
In riscv64 only `i64` is legal because registers are 64-bit and instructions operate with all the bits of the GPRs.

In other words, the current assortment of instructions that would be useable to implement 32-bit operations (there are just a few of them) is not broad enough to warrant making `i32` legal in RISC-V.


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  https://reviews.llvm.org/D68360/new/

https://reviews.llvm.org/D68360