[PATCH] D68686: [X86] Add strict fp support for instructions fadd/fsub/fmul/fdiv

[Pengfei Wang via Phabricator via llvm-commits]

pengfei created this revision.
pengfei added reviewers: craig.topper, RKSimon, andrew.w.kaylor, uweigand, kpn, spatel, cameron.mcinally.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

This patch adds MXCSR as a reserved physical register and models its use
by releated instructions. It also adds flag "mayRaiseFPException" for them.

Following what SystemZ and other targets does, only the current rounding
modes and the IEEE exception masks are modeled. *Changes* of the MXCSR
due to exceptions are not modeled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68686

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/CodeGen/MIR/X86/constant-pool.mir
  llvm/test/CodeGen/MIR/X86/fastmath.mir
  llvm/test/CodeGen/MIR/X86/memory-operands.mir
  llvm/test/CodeGen/X86/evex-to-vex-compress.mir
  llvm/test/CodeGen/X86/fp-strict-avx.ll
  llvm/test/CodeGen/X86/fp-strict-avx512.ll
  llvm/test/CodeGen/X86/fp-strict-sse.ll
  llvm/test/CodeGen/X86/ipra-reg-usage.ll
  llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

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