[PATCH] D68667: [SLP] respect target register width for GEP vectorization (PR43578)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, xbolva00, ABataev.
Herald added subscribers: hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

We failed to account for the target register width (max vector factor) when vectorizing starting from GEPs. This causes vectorization to proceed to obviously illegal widths as in:
https://bugs.llvm.org/show_bug.cgi?id=43578

For x86, this also means that SLP can produce rogue AVX or AVX512 code even when the user specifies a narrower vector width.

The AArch64 test in ext-trunc.ll appears to be better using the narrower width. I'm not exactly sure what getelementptr.ll is trying to do, but it's testing with "-slp-threshold=-18", so I'm not worried about those diffs. The x86 test is an over-reduction from SPEC h264; this patch appears to restore the perf loss caused by SLP when using -march=haswell.


https://reviews.llvm.org/D68667

Files:
  llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
  llvm/test/Transforms/SLPVectorizer/AArch64/ext-trunc.ll
  llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
  llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll

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