[PATCH] D68651: [InstCombine] Signed saturation patterns

[Hideki Saito via Phabricator via llvm-commits]

hsaito added a comment.

In D68651#1699976 <https://reviews.llvm.org/D68651#1699976>, @dmgreen wrote:

> We do form uadd_sat as in rL357012 <https://reviews.llvm.org/rL357012> and usub_sat from selects.
>
> I really just need some way to generate sadd_sats for vectorisation. If there's a better way than this, I'm all ears :)


If we just need vectorization with saturating add to happen, we just need a better pattern matcher utility. There should be benefits for going to intrinsic that compensates for the possible loss of optimizations that we might get with a sequence of Instructions.  Is this (i.e., saturating add/sub intrinsic as the canonical form) something already discussed in llvm-dev that I missed? When I was involved in the "vector idioms" discussion few years ago, general consensus (among 10+ people interested in that topic) was that we need better pattern matchers than pushing for vector idiom specific intrinsics. That's why I'm asking.

The same question also applies to rL357012 <https://reviews.llvm.org/rL357012>.


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