[PATCH] D68203: [SelectionDAG][SVE] Add ISD node for VSCALE.

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

What happens if we see IR like:

  %1 = mul i16 vscale, -2

Would that be promoted to i32 through `PromoteIntRes_VSCALE(...)`?



================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5141
+    }
+    LLVM_FALLTHROUGH;
   case ISD::SRA:
----------------
This should probably have a test. Same for ISD::MUL.


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  https://reviews.llvm.org/D68203/new/

https://reviews.llvm.org/D68203