[llvm] r374040 - MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block

[Nicolai Haehnle via llvm-commits]

Author: nha
Date: Tue Oct  8 05:46:20 2019
New Revision: 374040

URL: http://llvm.org/viewvc/llvm-project?rev=374040&view=rev
Log:
MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block

Summary:
When getValueInMiddleOfBlock happens to be called for a basic block
that has no incoming value at all, an IMPLICIT_DEF is inserted in that
block via GetValueAtEndOfBlockInternal. This IMPLICIT_DEF must be at
the top of its basic block or it will likely not reach the use that
the caller intends to insert.

Issue: https://github.com/GPUOpen-Drivers/llpc/issues/204

Reviewers: arsenm, rampitec

Subscribers: jvesely, wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68183

Added:
    llvm/trunk/test/CodeGen/AMDGPU/si-i1-copies.mir
Modified:
    llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp

Modified: llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp?rev=374040&r1=374039&r2=374040&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineSSAUpdater.cpp Tue Oct  8 05:46:20 2019
@@ -292,7 +292,7 @@ public:
                               MachineSSAUpdater *Updater) {
     // Insert an implicit_def to represent an undef value.
     MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
-                                        BB, BB->getFirstTerminator(),
+                                        BB, BB->getFirstNonPHI(),
                                         Updater->VRC, Updater->MRI,
                                         Updater->TII);
     return NewDef->getOperand(0).getReg();

Added: llvm/trunk/test/CodeGen/AMDGPU/si-i1-copies.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-i1-copies.mir?rev=374040&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-i1-copies.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/si-i1-copies.mir Tue Oct  8 05:46:20 2019
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=si-i1-copies -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
+
+# Test that the new IMPLICIT_DEF is inserted in the correct location.
+---
+name:            test_undef
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: test_undef
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.1(0x80000000)
+  ; GCN:   S_BRANCH %bb.1
+  ; GCN: bb.1:
+  ; GCN:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; GCN:   [[COPY:%[0-9]+]]:sreg_64_xexec = COPY [[DEF]]
+  ; GCN:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[COPY]], implicit $exec
+  bb.0:
+    successors: %bb.1
+
+    %0:vreg_1 = IMPLICIT_DEF
+    S_BRANCH %bb.1
+
+  bb.1:
+    %1:vreg_1 = PHI %0, %bb.0
+    %2:sreg_64_xexec = COPY %1
+    %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2, implicit $exec
+
+...