[PATCH] D68625: [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: hfinkel, PowerPC, aemerson, efriedma.
Herald added subscribers: wuzish, hiraditya, kristof.beyls.
Herald added a project: LLVM.

For below test case, we will get assert error except for AArch64 and ARM:

declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
define i8 @test_v3i8(<3 x i8> %a) nounwind {

  %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
  ret i8 %b

}
This patch is fix below error when the number of element is not power of 2 for those llvm.experimental.vector.reduce.* function.


https://reviews.llvm.org/D68625

Files:
  llvm/lib/CodeGen/ExpandReductions.cpp
  llvm/test/CodeGen/Generic/expand-experimental-reductions.ll


Index: llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
===================================================================
--- llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
+++ llvm/test/CodeGen/Generic/expand-experimental-reductions.ll
@@ -18,6 +18,7 @@
 declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double>)
 declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double>)
 
+declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8>)
 
 define i64 @add_i64(<2 x i64> %vec) {
 ; CHECK-LABEL: @add_i64(
@@ -303,3 +304,15 @@
   %r = call double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %vec)
   ret double %r
 }
+
+; Test when the vector size is not power of two.
+define i8 @test_v3i8(<3 x i8> %a) nounwind {
+; CHECK-LABEL: @test_v3i8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    %b = call i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a)
+; CHECK-NEXT:    ret i8 %b
+;
+entry:
+  %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
+  ret i8 %b
+}
Index: llvm/lib/CodeGen/ExpandReductions.cpp
===================================================================
--- llvm/lib/CodeGen/ExpandReductions.cpp
+++ llvm/lib/CodeGen/ExpandReductions.cpp
@@ -105,6 +105,9 @@
       if (!FMF.allowReassoc())
         Rdx = getOrderedReduction(Builder, Acc, Vec, getOpcode(ID), MRK);
       else {
+        if (!isPowerOf2_32(Vec->getType()->getVectorNumElements()))
+          continue;
+
         Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), MRK);
         Rdx = Builder.CreateBinOp((Instruction::BinaryOps)getOpcode(ID),
                                   Acc, Rdx, "bin.rdx");
@@ -122,6 +125,9 @@
     case Intrinsic::experimental_vector_reduce_fmax:
     case Intrinsic::experimental_vector_reduce_fmin: {
       Value *Vec = II->getArgOperand(0);
+      if (!isPowerOf2_32(Vec->getType()->getVectorNumElements()))
+        continue;
+
       Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), MRK);
     } break;
     default:


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