[llvm] r373944 - AMDGPU/GlobalISel: Select VALU G_AMDGPU_FFBH_U32

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Oct  7 12:10:43 2019
New Revision: 373944

URL: http://llvm.org/viewvc/llvm-project?rev=373944&view=rev
Log:
AMDGPU/GlobalISel: Select VALU G_AMDGPU_FFBH_U32

Modified:
    llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir

Modified: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td?rev=373944&r1=373943&r2=373944&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td Mon Oct  7 12:10:43 2019
@@ -235,7 +235,7 @@ defm V_COS_F32 : VOP1Inst <"v_cos_f32",
 
 defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>;
 defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, bitreverse>;
-defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32>;
+defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32, AMDGPUffbh_u32>;
 defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32>;
 defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32, AMDGPUffbh_i32>;
 

Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir?rev=373944&r1=373943&r2=373944&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir Mon Oct  7 12:10:43 2019
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 ---
 
@@ -36,9 +36,9 @@ body: |
 
     ; CHECK-LABEL: name: ffbh_u32_s32_v_v
     ; CHECK: liveins: $vgpr0
-    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
-    ; CHECK: S_ENDPGM 0, implicit [[AMDGPU_FFBH_U32_]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; CHECK: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
+    ; CHECK: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
   %0:vgpr(s32) = COPY $vgpr0
   %1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
   S_ENDPGM 0, implicit %1
@@ -58,9 +58,9 @@ body: |
 
     ; CHECK-LABEL: name: ffbh_u32_v_s
     ; CHECK: liveins: $sgpr0
-    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)
-    ; CHECK: S_ENDPGM 0, implicit [[AMDGPU_FFBH_U32_]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; CHECK: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
+    ; CHECK: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
   %0:sgpr(s32) = COPY $sgpr0
   %1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
   S_ENDPGM 0, implicit %1