[PATCH] D68583: AMDGPU: Fix i16 arithmetic pattern redundancy

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kzhuravl.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely.

There were 2 problems here. First, these patterns were duplicated to
handle the inverted shift operands instead of using the commuted
PatFrags.

      

Second, the point of the zext folding patterns don't apply to the
non-0ing high subtargets. They should be skipped instead of inserting
the extension. The zeroing high code would be emitted when necessary
anyway. This was also emitting unnecessary zexts in cases where the
high bits were undefined.


https://reviews.llvm.org/D68583

Files:
  lib/Target/AMDGPU/VOP2Instructions.td
  test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
  test/CodeGen/AMDGPU/idot2.ll
  test/CodeGen/AMDGPU/idot4s.ll
  test/CodeGen/AMDGPU/idot4u.ll
  test/CodeGen/AMDGPU/idot8s.ll
  test/CodeGen/AMDGPU/idot8u.ll
  test/CodeGen/AMDGPU/preserve-hi16.ll
  test/CodeGen/AMDGPU/sdwa-peephole.ll

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