[llvm] r373907 - [Mips] Always save RA when disabling frame pointer elimination
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 7 07:01:38 PDT 2019
Author: atanasyan
Date: Mon Oct 7 07:01:37 2019
New Revision: 373907
URL: http://llvm.org/viewvc/llvm-project?rev=373907&view=rev
Log:
[Mips] Always save RA when disabling frame pointer elimination
This ensures that frame-based unwinding will continue to work when
calling a noreturn function; there is not much use having the caller's
frame pointer saved if you don't also have the caller's program counter.
Patch by James Clarke.
Differential Revision: https://reviews.llvm.org/D68542
Added:
llvm/trunk/test/CodeGen/Mips/no-frame-pointer-elim.ll
Modified:
llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
llvm/trunk/test/CodeGen/Mips/cconv/vector.ll
llvm/trunk/test/CodeGen/Mips/dynamic-stack-realignment.ll
llvm/trunk/test/CodeGen/Mips/frame-address.ll
llvm/trunk/test/CodeGen/Mips/tnaked.ll
llvm/trunk/test/CodeGen/Mips/v2i16tof32.ll
Modified: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp?rev=373907&r1=373906&r2=373907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp Mon Oct 7 07:01:37 2019
@@ -865,12 +865,15 @@ void MipsSEFrameLowering::determineCalle
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
MipsABIInfo ABI = STI.getABI();
+ unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
unsigned FP = ABI.GetFramePtr();
unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;
- // Mark $fp as used if function has dedicated frame pointer.
- if (hasFP(MF))
+ // Mark $ra and $fp as used if function has dedicated frame pointer.
+ if (hasFP(MF)) {
+ setAliasRegs(MF, SavedRegs, RA);
setAliasRegs(MF, SavedRegs, FP);
+ }
// Mark $s7 as used if function has dedicated base pointer.
if (hasBP(MF))
setAliasRegs(MF, SavedRegs, BP);
Modified: llvm/trunk/test/CodeGen/Mips/cconv/vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=373907&r1=373906&r2=373907&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/vector.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cconv/vector.ll Mon Oct 7 07:01:37 2019
@@ -50,23 +50,25 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x
;
; MIPS32R5EB-LABEL: i8_2:
; MIPS32R5EB: # %bb.0:
-; MIPS32R5EB-NEXT: addiu $sp, $sp, -48
-; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EB-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: addiu $sp, $sp, -64
+; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 64
+; MIPS32R5EB-NEXT: sw $ra, 60($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 56($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
; MIPS32R5EB-NEXT: and $sp, $sp, $1
-; MIPS32R5EB-NEXT: sw $5, 36($sp)
-; MIPS32R5EB-NEXT: sw $4, 40($sp)
-; MIPS32R5EB-NEXT: lbu $1, 37($sp)
+; MIPS32R5EB-NEXT: sw $5, 48($sp)
+; MIPS32R5EB-NEXT: sw $4, 52($sp)
+; MIPS32R5EB-NEXT: lbu $1, 49($sp)
; MIPS32R5EB-NEXT: sw $1, 28($sp)
-; MIPS32R5EB-NEXT: lbu $1, 36($sp)
+; MIPS32R5EB-NEXT: lbu $1, 48($sp)
; MIPS32R5EB-NEXT: sw $1, 20($sp)
-; MIPS32R5EB-NEXT: lbu $1, 41($sp)
+; MIPS32R5EB-NEXT: lbu $1, 53($sp)
; MIPS32R5EB-NEXT: sw $1, 12($sp)
-; MIPS32R5EB-NEXT: lbu $1, 40($sp)
+; MIPS32R5EB-NEXT: lbu $1, 52($sp)
; MIPS32R5EB-NEXT: sw $1, 4($sp)
; MIPS32R5EB-NEXT: ld.d $w0, 16($sp)
; MIPS32R5EB-NEXT: ld.d $w1, 0($sp)
@@ -74,12 +76,13 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[3]
-; MIPS32R5EB-NEXT: sb $2, 33($sp)
-; MIPS32R5EB-NEXT: sb $1, 32($sp)
-; MIPS32R5EB-NEXT: lhu $2, 32($sp)
+; MIPS32R5EB-NEXT: sb $2, 45($sp)
+; MIPS32R5EB-NEXT: sb $1, 44($sp)
+; MIPS32R5EB-NEXT: lhu $2, 44($sp)
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
-; MIPS32R5EB-NEXT: addiu $sp, $sp, 48
+; MIPS32R5EB-NEXT: lw $fp, 56($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 60($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: addiu $sp, $sp, 64
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
;
@@ -151,35 +154,38 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x
;
; MIPS32R5EL-LABEL: i8_2:
; MIPS32R5EL: # %bb.0:
-; MIPS32R5EL-NEXT: addiu $sp, $sp, -48
-; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EL-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: addiu $sp, $sp, -64
+; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 64
+; MIPS32R5EL-NEXT: sw $ra, 60($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 56($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
; MIPS32R5EL-NEXT: and $sp, $sp, $1
-; MIPS32R5EL-NEXT: sw $5, 36($sp)
-; MIPS32R5EL-NEXT: sw $4, 40($sp)
-; MIPS32R5EL-NEXT: lbu $1, 37($sp)
+; MIPS32R5EL-NEXT: sw $5, 48($sp)
+; MIPS32R5EL-NEXT: sw $4, 52($sp)
+; MIPS32R5EL-NEXT: lbu $1, 49($sp)
; MIPS32R5EL-NEXT: sw $1, 24($sp)
-; MIPS32R5EL-NEXT: lbu $1, 36($sp)
+; MIPS32R5EL-NEXT: lbu $1, 48($sp)
; MIPS32R5EL-NEXT: sw $1, 16($sp)
-; MIPS32R5EL-NEXT: lbu $1, 41($sp)
+; MIPS32R5EL-NEXT: lbu $1, 53($sp)
; MIPS32R5EL-NEXT: sw $1, 8($sp)
-; MIPS32R5EL-NEXT: lbu $1, 40($sp)
+; MIPS32R5EL-NEXT: lbu $1, 52($sp)
; MIPS32R5EL-NEXT: sw $1, 0($sp)
; MIPS32R5EL-NEXT: ld.d $w0, 16($sp)
; MIPS32R5EL-NEXT: ld.d $w1, 0($sp)
; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
-; MIPS32R5EL-NEXT: sb $2, 33($sp)
-; MIPS32R5EL-NEXT: sb $1, 32($sp)
-; MIPS32R5EL-NEXT: lhu $2, 32($sp)
+; MIPS32R5EL-NEXT: sb $2, 45($sp)
+; MIPS32R5EL-NEXT: sb $1, 44($sp)
+; MIPS32R5EL-NEXT: lhu $2, 44($sp)
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
-; MIPS32R5EL-NEXT: addiu $sp, $sp, 48
+; MIPS32R5EL-NEXT: lw $fp, 56($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 60($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: addiu $sp, $sp, 64
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
;
@@ -312,36 +318,38 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2
; MIPS32R5EB: # %bb.0: # %entry
; MIPS32R5EB-NEXT: addiu $sp, $sp, -144
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 144
-; MIPS32R5EB-NEXT: sw $fp, 140($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 140($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 136($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
; MIPS32R5EB-NEXT: and $sp, $sp, $1
-; MIPS32R5EB-NEXT: sw $5, 132($sp)
-; MIPS32R5EB-NEXT: sw $4, 136($sp)
-; MIPS32R5EB-NEXT: lbu $1, 133($sp)
+; MIPS32R5EB-NEXT: sw $5, 128($sp)
+; MIPS32R5EB-NEXT: sw $4, 132($sp)
+; MIPS32R5EB-NEXT: lbu $1, 129($sp)
; MIPS32R5EB-NEXT: sw $1, 76($sp)
-; MIPS32R5EB-NEXT: lbu $1, 132($sp)
+; MIPS32R5EB-NEXT: lbu $1, 128($sp)
; MIPS32R5EB-NEXT: sw $1, 68($sp)
-; MIPS32R5EB-NEXT: lbu $1, 137($sp)
+; MIPS32R5EB-NEXT: lbu $1, 133($sp)
; MIPS32R5EB-NEXT: sw $1, 60($sp)
-; MIPS32R5EB-NEXT: lbu $1, 136($sp)
+; MIPS32R5EB-NEXT: lbu $1, 132($sp)
; MIPS32R5EB-NEXT: sw $1, 52($sp)
; MIPS32R5EB-NEXT: ld.d $w0, 64($sp)
; MIPS32R5EB-NEXT: ld.d $w1, 48($sp)
; MIPS32R5EB-NEXT: addv.d $w0, $w1, $w0
-; MIPS32R5EB-NEXT: sw $6, 128($sp)
-; MIPS32R5EB-NEXT: lbu $1, 129($sp)
+; MIPS32R5EB-NEXT: sw $6, 124($sp)
+; MIPS32R5EB-NEXT: lbu $1, 125($sp)
; MIPS32R5EB-NEXT: sw $1, 92($sp)
-; MIPS32R5EB-NEXT: lbu $1, 128($sp)
+; MIPS32R5EB-NEXT: lbu $1, 124($sp)
; MIPS32R5EB-NEXT: sw $1, 84($sp)
; MIPS32R5EB-NEXT: ld.d $w1, 80($sp)
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
-; MIPS32R5EB-NEXT: sw $7, 124($sp)
-; MIPS32R5EB-NEXT: lbu $1, 125($sp)
+; MIPS32R5EB-NEXT: sw $7, 120($sp)
+; MIPS32R5EB-NEXT: lbu $1, 121($sp)
; MIPS32R5EB-NEXT: sw $1, 108($sp)
-; MIPS32R5EB-NEXT: lbu $1, 124($sp)
+; MIPS32R5EB-NEXT: lbu $1, 120($sp)
; MIPS32R5EB-NEXT: sw $1, 100($sp)
; MIPS32R5EB-NEXT: ld.d $w1, 96($sp)
; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
@@ -366,11 +374,12 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[3]
-; MIPS32R5EB-NEXT: sb $2, 121($sp)
-; MIPS32R5EB-NEXT: sb $1, 120($sp)
-; MIPS32R5EB-NEXT: lhu $2, 120($sp)
+; MIPS32R5EB-NEXT: sb $2, 117($sp)
+; MIPS32R5EB-NEXT: sb $1, 116($sp)
+; MIPS32R5EB-NEXT: lhu $2, 116($sp)
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 140($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 136($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 140($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 144
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -550,36 +559,38 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2
; MIPS32R5EL: # %bb.0: # %entry
; MIPS32R5EL-NEXT: addiu $sp, $sp, -144
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 144
-; MIPS32R5EL-NEXT: sw $fp, 140($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 140($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 136($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
; MIPS32R5EL-NEXT: and $sp, $sp, $1
-; MIPS32R5EL-NEXT: sw $5, 132($sp)
-; MIPS32R5EL-NEXT: sw $4, 136($sp)
-; MIPS32R5EL-NEXT: lbu $1, 133($sp)
+; MIPS32R5EL-NEXT: sw $5, 128($sp)
+; MIPS32R5EL-NEXT: sw $4, 132($sp)
+; MIPS32R5EL-NEXT: lbu $1, 129($sp)
; MIPS32R5EL-NEXT: sw $1, 72($sp)
-; MIPS32R5EL-NEXT: lbu $1, 132($sp)
+; MIPS32R5EL-NEXT: lbu $1, 128($sp)
; MIPS32R5EL-NEXT: sw $1, 64($sp)
-; MIPS32R5EL-NEXT: lbu $1, 137($sp)
+; MIPS32R5EL-NEXT: lbu $1, 133($sp)
; MIPS32R5EL-NEXT: sw $1, 56($sp)
-; MIPS32R5EL-NEXT: lbu $1, 136($sp)
+; MIPS32R5EL-NEXT: lbu $1, 132($sp)
; MIPS32R5EL-NEXT: sw $1, 48($sp)
; MIPS32R5EL-NEXT: ld.d $w0, 64($sp)
; MIPS32R5EL-NEXT: ld.d $w1, 48($sp)
; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
-; MIPS32R5EL-NEXT: sw $6, 128($sp)
-; MIPS32R5EL-NEXT: lbu $1, 129($sp)
+; MIPS32R5EL-NEXT: sw $6, 124($sp)
+; MIPS32R5EL-NEXT: lbu $1, 125($sp)
; MIPS32R5EL-NEXT: sw $1, 88($sp)
-; MIPS32R5EL-NEXT: lbu $1, 128($sp)
+; MIPS32R5EL-NEXT: lbu $1, 124($sp)
; MIPS32R5EL-NEXT: sw $1, 80($sp)
; MIPS32R5EL-NEXT: ld.d $w1, 80($sp)
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
-; MIPS32R5EL-NEXT: sw $7, 124($sp)
-; MIPS32R5EL-NEXT: lbu $1, 125($sp)
+; MIPS32R5EL-NEXT: sw $7, 120($sp)
+; MIPS32R5EL-NEXT: lbu $1, 121($sp)
; MIPS32R5EL-NEXT: sw $1, 104($sp)
-; MIPS32R5EL-NEXT: lbu $1, 124($sp)
+; MIPS32R5EL-NEXT: lbu $1, 120($sp)
; MIPS32R5EL-NEXT: sw $1, 96($sp)
; MIPS32R5EL-NEXT: ld.d $w1, 96($sp)
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
@@ -603,11 +614,12 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2
; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
-; MIPS32R5EL-NEXT: sb $2, 121($sp)
-; MIPS32R5EL-NEXT: sb $1, 120($sp)
-; MIPS32R5EL-NEXT: lhu $2, 120($sp)
+; MIPS32R5EL-NEXT: sb $2, 117($sp)
+; MIPS32R5EL-NEXT: sb $1, 116($sp)
+; MIPS32R5EL-NEXT: lhu $2, 116($sp)
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 140($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 136($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 140($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 144
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -952,8 +964,10 @@ define <8 x i8> @i8_8(<8 x i8> %a, <8 x
; MIPS32R5EB: # %bb.0:
; MIPS32R5EB-NEXT: addiu $sp, $sp, -48
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EB-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
@@ -1019,7 +1033,8 @@ define <8 x i8> @i8_8(<8 x i8> %a, <8 x
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $3, $w0[3]
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 48
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -1088,8 +1103,10 @@ define <8 x i8> @i8_8(<8 x i8> %a, <8 x
; MIPS32R5EL: # %bb.0:
; MIPS32R5EL-NEXT: addiu $sp, $sp, -48
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EL-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
@@ -1155,7 +1172,8 @@ define <8 x i8> @i8_8(<8 x i8> %a, <8 x
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $3, $w0[2]
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 48
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -1471,23 +1489,25 @@ define <2 x i16> @i16_2(<2 x i16> %a, <2
;
; MIPS32R5EB-LABEL: i16_2:
; MIPS32R5EB: # %bb.0:
-; MIPS32R5EB-NEXT: addiu $sp, $sp, -48
-; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EB-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: addiu $sp, $sp, -64
+; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 64
+; MIPS32R5EB-NEXT: sw $ra, 60($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 56($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
; MIPS32R5EB-NEXT: and $sp, $sp, $1
-; MIPS32R5EB-NEXT: sw $5, 36($sp)
-; MIPS32R5EB-NEXT: sw $4, 40($sp)
-; MIPS32R5EB-NEXT: lhu $1, 38($sp)
+; MIPS32R5EB-NEXT: sw $5, 48($sp)
+; MIPS32R5EB-NEXT: sw $4, 52($sp)
+; MIPS32R5EB-NEXT: lhu $1, 50($sp)
; MIPS32R5EB-NEXT: sw $1, 28($sp)
-; MIPS32R5EB-NEXT: lhu $1, 36($sp)
+; MIPS32R5EB-NEXT: lhu $1, 48($sp)
; MIPS32R5EB-NEXT: sw $1, 20($sp)
-; MIPS32R5EB-NEXT: lhu $1, 42($sp)
+; MIPS32R5EB-NEXT: lhu $1, 54($sp)
; MIPS32R5EB-NEXT: sw $1, 12($sp)
-; MIPS32R5EB-NEXT: lhu $1, 40($sp)
+; MIPS32R5EB-NEXT: lhu $1, 52($sp)
; MIPS32R5EB-NEXT: sw $1, 4($sp)
; MIPS32R5EB-NEXT: ld.d $w0, 16($sp)
; MIPS32R5EB-NEXT: ld.d $w1, 0($sp)
@@ -1495,12 +1515,13 @@ define <2 x i16> @i16_2(<2 x i16> %a, <2
; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[3]
-; MIPS32R5EB-NEXT: sh $2, 34($sp)
-; MIPS32R5EB-NEXT: sh $1, 32($sp)
-; MIPS32R5EB-NEXT: lw $2, 32($sp)
+; MIPS32R5EB-NEXT: sh $2, 46($sp)
+; MIPS32R5EB-NEXT: sh $1, 44($sp)
+; MIPS32R5EB-NEXT: lw $2, 44($sp)
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
-; MIPS32R5EB-NEXT: addiu $sp, $sp, 48
+; MIPS32R5EB-NEXT: lw $fp, 56($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 60($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: addiu $sp, $sp, 64
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
;
@@ -1532,35 +1553,38 @@ define <2 x i16> @i16_2(<2 x i16> %a, <2
;
; MIPS32R5EL-LABEL: i16_2:
; MIPS32R5EL: # %bb.0:
-; MIPS32R5EL-NEXT: addiu $sp, $sp, -48
-; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EL-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: addiu $sp, $sp, -64
+; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 64
+; MIPS32R5EL-NEXT: sw $ra, 60($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 56($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
; MIPS32R5EL-NEXT: and $sp, $sp, $1
-; MIPS32R5EL-NEXT: sw $5, 36($sp)
-; MIPS32R5EL-NEXT: sw $4, 40($sp)
-; MIPS32R5EL-NEXT: lhu $1, 38($sp)
+; MIPS32R5EL-NEXT: sw $5, 48($sp)
+; MIPS32R5EL-NEXT: sw $4, 52($sp)
+; MIPS32R5EL-NEXT: lhu $1, 50($sp)
; MIPS32R5EL-NEXT: sw $1, 24($sp)
-; MIPS32R5EL-NEXT: lhu $1, 36($sp)
+; MIPS32R5EL-NEXT: lhu $1, 48($sp)
; MIPS32R5EL-NEXT: sw $1, 16($sp)
-; MIPS32R5EL-NEXT: lhu $1, 42($sp)
+; MIPS32R5EL-NEXT: lhu $1, 54($sp)
; MIPS32R5EL-NEXT: sw $1, 8($sp)
-; MIPS32R5EL-NEXT: lhu $1, 40($sp)
+; MIPS32R5EL-NEXT: lhu $1, 52($sp)
; MIPS32R5EL-NEXT: sw $1, 0($sp)
; MIPS32R5EL-NEXT: ld.d $w0, 16($sp)
; MIPS32R5EL-NEXT: ld.d $w1, 0($sp)
; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
-; MIPS32R5EL-NEXT: sh $2, 34($sp)
-; MIPS32R5EL-NEXT: sh $1, 32($sp)
-; MIPS32R5EL-NEXT: lw $2, 32($sp)
+; MIPS32R5EL-NEXT: sh $2, 46($sp)
+; MIPS32R5EL-NEXT: sh $1, 44($sp)
+; MIPS32R5EL-NEXT: lw $2, 44($sp)
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
-; MIPS32R5EL-NEXT: addiu $sp, $sp, 48
+; MIPS32R5EL-NEXT: lw $fp, 56($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 60($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: addiu $sp, $sp, 64
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
%1 = add <2 x i16> %a, %b
@@ -1622,8 +1646,10 @@ define <4 x i16> @i16_4(<4 x i16> %a, <4
; MIPS32R5EB: # %bb.0:
; MIPS32R5EB-NEXT: addiu $sp, $sp, -48
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EB-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
@@ -1665,7 +1691,8 @@ define <4 x i16> @i16_4(<4 x i16> %a, <4
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $3, $w0[3]
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 48
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -1710,8 +1737,10 @@ define <4 x i16> @i16_4(<4 x i16> %a, <4
; MIPS32R5EL: # %bb.0:
; MIPS32R5EL-NEXT: addiu $sp, $sp, -48
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EL-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
@@ -1753,7 +1782,8 @@ define <4 x i16> @i16_4(<4 x i16> %a, <4
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $3, $w0[2]
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 48
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -1962,8 +1992,10 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2
; MIPS32R5EB: # %bb.0:
; MIPS32R5EB-NEXT: addiu $sp, $sp, -48
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EB-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
@@ -1979,7 +2011,8 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $3, $w0[3]
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 48
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -2010,8 +2043,10 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2
; MIPS32R5EL: # %bb.0:
; MIPS32R5EL-NEXT: addiu $sp, $sp, -48
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5EL-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
@@ -2026,7 +2061,8 @@ define <2 x i32> @i32_2(<2 x i32> %a, <2
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $3, $w0[2]
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 48
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -2312,8 +2348,10 @@ define void @float_2(<2 x float> %a, <2
; MIPS32R5: # %bb.0:
; MIPS32R5-NEXT: addiu $sp, $sp, -48
; MIPS32R5-NEXT: .cfi_def_cfa_offset 48
-; MIPS32R5-NEXT: sw $fp, 44($sp) # 4-byte Folded Spill
-; MIPS32R5-NEXT: .cfi_offset 30, -4
+; MIPS32R5-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; MIPS32R5-NEXT: sw $fp, 40($sp) # 4-byte Folded Spill
+; MIPS32R5-NEXT: .cfi_offset 31, -4
+; MIPS32R5-NEXT: .cfi_offset 30, -8
; MIPS32R5-NEXT: move $fp, $sp
; MIPS32R5-NEXT: .cfi_def_cfa_register 30
; MIPS32R5-NEXT: addiu $1, $zero, -16
@@ -2331,7 +2369,8 @@ define void @float_2(<2 x float> %a, <2
; MIPS32R5-NEXT: swc1 $f1, 4($2)
; MIPS32R5-NEXT: swc1 $f0, %lo(float_res_v2f32)($1)
; MIPS32R5-NEXT: move $sp, $fp
-; MIPS32R5-NEXT: lw $fp, 44($sp) # 4-byte Folded Reload
+; MIPS32R5-NEXT: lw $fp, 40($sp) # 4-byte Folded Reload
+; MIPS32R5-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
; MIPS32R5-NEXT: addiu $sp, $sp, 48
; MIPS32R5-NEXT: jr $ra
; MIPS32R5-NEXT: nop
@@ -2794,8 +2833,10 @@ define <8 x i8> @ret_8_i8() {
; MIPS32R5EB: # %bb.0:
; MIPS32R5EB-NEXT: addiu $sp, $sp, -32
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 32
-; MIPS32R5EB-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
@@ -2810,7 +2851,8 @@ define <8 x i8> @ret_8_i8() {
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $3, $w0[3]
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 32
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -2829,8 +2871,10 @@ define <8 x i8> @ret_8_i8() {
; MIPS32R5EL: # %bb.0:
; MIPS32R5EL-NEXT: addiu $sp, $sp, -32
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 32
-; MIPS32R5EL-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
@@ -2845,7 +2889,8 @@ define <8 x i8> @ret_8_i8() {
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $3, $w0[2]
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 32
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -2965,8 +3010,10 @@ define <4 x i16> @ret_4_i16() {
; MIPS32R5EB: # %bb.0:
; MIPS32R5EB-NEXT: addiu $sp, $sp, -32
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 32
-; MIPS32R5EB-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
@@ -2981,7 +3028,8 @@ define <4 x i16> @ret_4_i16() {
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $3, $w0[3]
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 32
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -3000,8 +3048,10 @@ define <4 x i16> @ret_4_i16() {
; MIPS32R5EL: # %bb.0:
; MIPS32R5EL-NEXT: addiu $sp, $sp, -32
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 32
-; MIPS32R5EL-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
@@ -3016,7 +3066,8 @@ define <4 x i16> @ret_4_i16() {
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $3, $w0[2]
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 32
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -3098,8 +3149,10 @@ define <2 x i32> @ret_2_i32() {
; MIPS32R5EB: # %bb.0:
; MIPS32R5EB-NEXT: addiu $sp, $sp, -32
; MIPS32R5EB-NEXT: .cfi_def_cfa_offset 32
-; MIPS32R5EB-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; MIPS32R5EB-NEXT: .cfi_offset 30, -4
+; MIPS32R5EB-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; MIPS32R5EB-NEXT: .cfi_offset 31, -4
+; MIPS32R5EB-NEXT: .cfi_offset 30, -8
; MIPS32R5EB-NEXT: move $fp, $sp
; MIPS32R5EB-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EB-NEXT: addiu $1, $zero, -16
@@ -3114,7 +3167,8 @@ define <2 x i32> @ret_2_i32() {
; MIPS32R5EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5EB-NEXT: copy_s.w $3, $w0[3]
; MIPS32R5EB-NEXT: move $sp, $fp
-; MIPS32R5EB-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; MIPS32R5EB-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; MIPS32R5EB-NEXT: addiu $sp, $sp, 32
; MIPS32R5EB-NEXT: jr $ra
; MIPS32R5EB-NEXT: nop
@@ -3133,8 +3187,10 @@ define <2 x i32> @ret_2_i32() {
; MIPS32R5EL: # %bb.0:
; MIPS32R5EL-NEXT: addiu $sp, $sp, -32
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 32
-; MIPS32R5EL-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; MIPS32R5EL-NEXT: .cfi_offset 30, -4
+; MIPS32R5EL-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; MIPS32R5EL-NEXT: .cfi_offset 31, -4
+; MIPS32R5EL-NEXT: .cfi_offset 30, -8
; MIPS32R5EL-NEXT: move $fp, $sp
; MIPS32R5EL-NEXT: .cfi_def_cfa_register 30
; MIPS32R5EL-NEXT: addiu $1, $zero, -16
@@ -3149,7 +3205,8 @@ define <2 x i32> @ret_2_i32() {
; MIPS32R5EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5EL-NEXT: copy_s.w $3, $w0[2]
; MIPS32R5EL-NEXT: move $sp, $fp
-; MIPS32R5EL-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; MIPS32R5EL-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; MIPS32R5EL-NEXT: addiu $sp, $sp, 32
; MIPS32R5EL-NEXT: jr $ra
; MIPS32R5EL-NEXT: nop
@@ -6073,8 +6130,10 @@ define float @mixed_i8(<2 x float> %a, i
; MIPS32R5: # %bb.0: # %entry
; MIPS32R5-NEXT: addiu $sp, $sp, -64
; MIPS32R5-NEXT: .cfi_def_cfa_offset 64
-; MIPS32R5-NEXT: sw $fp, 60($sp) # 4-byte Folded Spill
-; MIPS32R5-NEXT: .cfi_offset 30, -4
+; MIPS32R5-NEXT: sw $ra, 60($sp) # 4-byte Folded Spill
+; MIPS32R5-NEXT: sw $fp, 56($sp) # 4-byte Folded Spill
+; MIPS32R5-NEXT: .cfi_offset 31, -4
+; MIPS32R5-NEXT: .cfi_offset 30, -8
; MIPS32R5-NEXT: move $fp, $sp
; MIPS32R5-NEXT: .cfi_def_cfa_register 30
; MIPS32R5-NEXT: addiu $1, $zero, -16
@@ -6098,7 +6157,8 @@ define float @mixed_i8(<2 x float> %a, i
; MIPS32R5-NEXT: splati.w $w1, $w0[1]
; MIPS32R5-NEXT: add.s $f0, $f0, $f1
; MIPS32R5-NEXT: move $sp, $fp
-; MIPS32R5-NEXT: lw $fp, 60($sp) # 4-byte Folded Reload
+; MIPS32R5-NEXT: lw $fp, 56($sp) # 4-byte Folded Reload
+; MIPS32R5-NEXT: lw $ra, 60($sp) # 4-byte Folded Reload
; MIPS32R5-NEXT: addiu $sp, $sp, 64
; MIPS32R5-NEXT: jr $ra
; MIPS32R5-NEXT: nop
Modified: llvm/trunk/test/CodeGen/Mips/dynamic-stack-realignment.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dynamic-stack-realignment.ll?rev=373907&r1=373906&r2=373907&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/dynamic-stack-realignment.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/dynamic-stack-realignment.ll Mon Oct 7 07:01:37 2019
@@ -163,8 +163,9 @@ entry:
; GP32-M: addiu $sp, $sp, -1024
; GP32-MMR2: addiusp -1024
; GP32-MMR6: addiu $sp, $sp, -1024
- ; GP32: sw $fp, 1020($sp)
- ; GP32: sw $23, 1016($sp)
+ ; GP32: sw $ra, 1020($sp)
+ ; GP32: sw $fp, 1016($sp)
+ ; GP32: sw $23, 1012($sp)
;
; GP32: move $fp, $sp
; GP32: addiu $[[T0:[0-9]+|gp]], $zero, -512
@@ -177,8 +178,9 @@ entry:
; epilogue
; GP32: move $sp, $fp
- ; GP32: lw $23, 1016($sp)
- ; GP32: lw $fp, 1020($sp)
+ ; GP32: lw $23, 1012($sp)
+ ; GP32: lw $fp, 1016($sp)
+ ; GP32: lw $ra, 1020($sp)
; GP32-M: addiu $sp, $sp, 1024
; GP32-MMR2: addiusp 1024
; GP32-MMR6: addiu $sp, $sp, 1024
@@ -201,8 +203,9 @@ entry:
; FIXME: We are currently over-allocating stack space.
; N32: addiu $sp, $sp, -1024
; N64: daddiu $sp, $sp, -1024
- ; GP64: sd $fp, 1016($sp)
- ; GP64: sd $23, 1008($sp)
+ ; GP64: sd $ra, 1016($sp)
+ ; GP64: sd $fp, 1008($sp)
+ ; GP64: sd $23, 1000($sp)
;
; GP64: move $fp, $sp
; GP64: addiu $[[T0:[0-9]+|gp]], $zero, -512
@@ -215,8 +218,9 @@ entry:
; epilogue
; GP64: move $sp, $fp
- ; GP64: ld $23, 1008($sp)
- ; GP64: ld $fp, 1016($sp)
+ ; GP64: ld $23, 1000($sp)
+ ; GP64: ld $fp, 1008($sp)
+ ; GP64: ld $ra, 1016($sp)
; N32: addiu $sp, $sp, 1024
; N64: daddiu $sp, $sp, 1024
Modified: llvm/trunk/test/CodeGen/Mips/frame-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/frame-address.ll?rev=373907&r1=373906&r2=373907&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/frame-address.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/frame-address.ll Mon Oct 7 07:01:37 2019
@@ -1,17 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=mipsel < %s | FileCheck %s
declare i8* @llvm.frameaddress(i32) nounwind readnone
define i8* @f() nounwind uwtable {
+; CHECK-LABEL: f:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $sp, $sp, -8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: sw $ra, 4($sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw $fp, 0($sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset 31, -4
+; CHECK-NEXT: .cfi_offset 30, -8
+; CHECK-NEXT: move $fp, $sp
+; CHECK-NEXT: .cfi_def_cfa_register 30
+; CHECK-NEXT: move $2, $fp
+; CHECK-NEXT: move $sp, $fp
+; CHECK-NEXT: lw $fp, 0($sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw $ra, 4($sp) # 4-byte Folded Reload
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: addiu $sp, $sp, 8
entry:
%0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0
-
-; CHECK: .cfi_startproc
-; CHECK: .cfi_def_cfa_offset 8
-; CHECK: .cfi_offset 30, -4
-; CHECK: move $fp, $sp
-; CHECK: .cfi_def_cfa_register 30
-; CHECK: move $2, $fp
-; CHECK: .cfi_endproc
}
Added: llvm/trunk/test/CodeGen/Mips/no-frame-pointer-elim.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/no-frame-pointer-elim.ll?rev=373907&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/no-frame-pointer-elim.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/no-frame-pointer-elim.ll Mon Oct 7 07:01:37 2019
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mips64 -relocation-model=static < %s \
+; RUN: | FileCheck %s --check-prefix STATIC
+; RUN: llc -march=mips64 -relocation-model=pic < %s \
+; RUN: | FileCheck %s --check-prefix PIC
+
+declare dso_local void @callee() noreturn nounwind
+
+define dso_local void @caller() nounwind "no-frame-pointer-elim-non-leaf" {
+; STATIC-LABEL: caller:
+; STATIC: # %bb.0: # %entry
+; STATIC-NEXT: daddiu $sp, $sp, -16
+; STATIC-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
+; STATIC-NEXT: sd $fp, 0($sp) # 8-byte Folded Spill
+; STATIC-NEXT: move $fp, $sp
+; STATIC-NEXT: jal callee
+; STATIC-NEXT: nop
+;
+; PIC-LABEL: caller:
+; PIC: # %bb.0: # %entry
+; PIC-NEXT: daddiu $sp, $sp, -32
+; PIC-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill
+; PIC-NEXT: sd $fp, 16($sp) # 8-byte Folded Spill
+; PIC-NEXT: sd $gp, 8($sp) # 8-byte Folded Spill
+; PIC-NEXT: move $fp, $sp
+; PIC-NEXT: lui $1, %hi(%neg(%gp_rel(caller)))
+; PIC-NEXT: daddu $1, $1, $25
+; PIC-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(caller)))
+; PIC-NEXT: ld $25, %call16(callee)($gp)
+; PIC-NEXT: .reloc .Ltmp0, R_MIPS_JALR, callee
+; PIC-NEXT: .Ltmp0:
+; PIC-NEXT: jalr $25
+; PIC-NEXT: nop
+entry:
+ tail call void @callee()
+ unreachable
+}
Modified: llvm/trunk/test/CodeGen/Mips/tnaked.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tnaked.ll?rev=373907&r1=373906&r2=373907&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/tnaked.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/tnaked.ll Mon Oct 7 07:01:37 2019
@@ -21,7 +21,7 @@ entry:
; CHECK: .ent tnonaked
; CHECK-LABEL: tnonaked:
; CHECK: .frame $fp,8,$ra
-; CHECK: .mask 0x40000000,-4
+; CHECK: .mask 0xc0000000,-4
; CHECK: .fmask 0x00000000,0
; CHECK: addiu $sp, $sp, -8
Modified: llvm/trunk/test/CodeGen/Mips/v2i16tof32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/v2i16tof32.ll?rev=373907&r1=373906&r2=373907&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/v2i16tof32.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/v2i16tof32.ll Mon Oct 7 07:01:37 2019
@@ -9,8 +9,10 @@ define float @f(<8 x i16>* %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addiu $sp, $sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: sw $fp, 28($sp) # 4-byte Folded Spill
-; CHECK-NEXT: .cfi_offset 30, -4
+; CHECK-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw $fp, 24($sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset 31, -4
+; CHECK-NEXT: .cfi_offset 30, -8
; CHECK-NEXT: move $fp, $sp
; CHECK-NEXT: .cfi_def_cfa_register 30
; CHECK-NEXT: addiu $1, $zero, -16
@@ -25,7 +27,8 @@ define float @f(<8 x i16>* %a) {
; CHECK-NEXT: sw $1, 4($sp)
; CHECK-NEXT: mtc1 $2, $f0
; CHECK-NEXT: move $sp, $fp
-; CHECK-NEXT: lw $fp, 28($sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw $fp, 24($sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
; CHECK-NEXT: jr $ra
; CHECK-NEXT: addiu $sp, $sp, 32
entry:
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