[PATCH] D68548: [Mips] Fix evaluating J-format branch targets

[James Clarke via Phabricator via llvm-commits]

jrtc27 created this revision.
jrtc27 added a reviewer: atanasyan.
Herald added subscribers: llvm-commits, hiraditya, arichardson, sdardis.
Herald added a project: LLVM.

J/JAL/JALX/JALS are absolute branches, but stay within the current
256 MB-aligned region, so we must include the high bits of the
instruction address when calculating the branch target.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68548

Files:
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/test/MC/Mips/micromips-jump-pc-region.s
  llvm/test/MC/Mips/mips-jump-pc-region.s


Index: llvm/test/MC/Mips/mips-jump-pc-region.s
===================================================================
--- /dev/null
+++ llvm/test/MC/Mips/mips-jump-pc-region.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple=mips -mcpu=mips32 -filetype=obj < %s \
+# RUN:   | llvm-objdump -d - | FileCheck %s
+# RUN: llvm-mc -triple=mips64 -mcpu=mips64 -filetype=obj < %s \
+# RUN:   | llvm-objdump -d - | FileCheck %s
+
+.set noreorder
+
+# Force us into the second 256 MB region with a non-zero instruction index
+.org 256*1024*1024 + 12
+# CHECK-LABEL: 1000000c foo:
+# CHECK-NEXT: 1000000c: 08 00 00 03                   j       12 <foo>
+# CHECK-NEXT: 10000010: 0c 00 00 04                   jal     16 <foo+0x4>
+# CHECK-NEXT: 10000014: 74 00 00 05                   jalx    20 <foo+0x8>
+foo:
+	j 12
+	jal 16
+	jalx 20
Index: llvm/test/MC/Mips/micromips-jump-pc-region.s
===================================================================
--- /dev/null
+++ llvm/test/MC/Mips/micromips-jump-pc-region.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple=mips -mcpu=mips32 -mattr=+micromips -filetype=obj < %s \
+# RUN:   | llvm-objdump -d - | FileCheck %s
+
+.set noreorder
+
+# Force us into the second 256 MB region with a non-zero instruction index
+.org 256*1024*1024 + 12
+# CHECK-LABEL: 1000000c foo:
+# CHECK-NEXT: 1000000c: d4 00 00 06                   j       12 <foo>
+# CHECK-NEXT: 10000010: f4 00 00 08                   jal     16 <foo+0x4>
+# CHECK-NEXT: 10000014: f0 00 00 05                   jalx    20 <foo+0x8>
+# CHECK-NEXT: 10000018: 74 00 00 0c                   jals    24 <foo+0xc>
+foo:
+	j 12
+	jal 16
+	jalx 20
+	jals 24
Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -141,14 +141,21 @@
     unsigned NumOps = Inst.getNumOperands();
     if (NumOps == 0)
       return false;
-    switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
+
+    unsigned Opcode = Inst.getOpcode();
+    switch (Info->get(Opcode).OpInfo[NumOps - 1].OperandType) {
     case MCOI::OPERAND_UNKNOWN:
     case MCOI::OPERAND_IMMEDIATE:
-      // jal, bal ...
-      Target = Inst.getOperand(NumOps - 1).getImm();
-      return true;
+      switch (Opcode) {
+      default:
+        // j, jal, jalx, jals
+        // Absolute branch within the current 256 MB-aligned region
+        uint64_t Region = Addr & ~uint64_t(0xfffffff);
+        Target = Region + Inst.getOperand(NumOps - 1).getImm();
+        return true;
+      }
     case MCOI::OPERAND_PCREL:
-      // b, j, beq ...
+      // b, beq ...
       Target = Addr + Inst.getOperand(NumOps - 1).getImm();
       return true;
     default:


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