[llvm] r373812 - [RISCV] Added missing ImmLeaf predicates

[Ana Pazos via llvm-commits]

Author: apazos
Date: Fri Oct  4 16:42:07 2019
New Revision: 373812

URL: http://llvm.org/viewvc/llvm-project?rev=373812&view=rev
Log:
[RISCV] Added missing ImmLeaf predicates

simm9_lsb0 and simm12_lsb0 operand types were missing predicates.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td?rev=373812&r1=373811&r2=373812&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td Fri Oct  4 16:42:07 2019
@@ -137,7 +137,8 @@ def uimm8_lsb000 : Operand<XLenVT>,
 }
 
 // A 9-bit signed immediate where the least significant bit is zero.
-def simm9_lsb0 : Operand<OtherVT> {
+def simm9_lsb0 : Operand<OtherVT>,
+                 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
@@ -196,7 +197,8 @@ def simm10_lsb0000nonzero : Operand<XLen
 }
 
 // A 12-bit signed immediate where the least significant bit is zero.
-def simm12_lsb0 : Operand<XLenVT> {
+def simm12_lsb0 : Operand<XLenVT>,
+                  ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<12>";