[PATCH] D68443: [PowerPC] Spill CR LT bits on P9 using setb

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: power-llvm-team, nemanjai, hfinkel, echristo.
Herald added subscribers: llvm-commits, shchenz, jsji, MaskRay, kbarton, hiraditya, qcolombet.
Herald added a project: LLVM.

This patch aims to spill CR[0-1]LT bits on POWER9 using the `setb` instruction.
The sequence on P9 <https://reviews.llvm.org/P9> to spill these bits will be:

  setb %reg, %CRREG
  stw %reg, $FI

Instead of the typical sequence:

  mfocrf %reg, %CRREG
  rlwinm %reg1, %reg, $SH, 0, 0
  stw %reg1, $FI

The number of `mfocrf` instructions within SPEC 2017 decreases by ~2.6%.


Repository:
  rL LLVM

https://reviews.llvm.org/D68443

Files:
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/spill_p9_setb.ll


Index: llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
@@ -0,0 +1,41 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
+; RUN:     | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
+; RUN:     | FileCheck %s
+
+define void @p9_setb_spill() {
+; CHECK-LABEL: p9_setb_spill:
+; CHECK:       # %bb.1: # %if.then
+; CHECK-DAG:    crnor 4*cr[[CREG:.*]]+lt, eq, eq
+; CHECK-NOT:    mfocrf [[REG2:.*]], [[CREG]]
+; CHECK-NOT:    rlwinm [[REG2]], [[REG2]]
+; CHECK-DAG:    setb [[REG1:.*]], cr[[CREG]]
+; CHECK-DAG:    stw [[REG1]]
+; CHECK:        blr
+; CHECK:        .LBB0_4: # %if.then1
+
+entry:
+  br i1 undef, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call signext i32 bitcast (i32 (...)* @fn_call to i32 ()*)()
+  %cmp1 = icmp ne i32 %call, 0
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %off0 = phi i1 [ %cmp1, %if.then ], [ false, %entry ]
+  tail call void asm sideeffect "#Clobber", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}"()
+  %off0.not = xor i1 %off0, true
+  %or = or i1 false, %off0.not
+  br i1 %or, label %if.end2, label %if.then1
+
+if.then1:                                         ; preds = %if.end
+  unreachable
+
+if.end2:                                         ; preds = %if.end
+  ret void
+}
+
+declare signext i32 @fn_call(...)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -778,6 +778,18 @@
       .addImm(-32768);
     break;
   default:
+    // On POWER9, spilling LT bits with the setb instruction is more efficient.
+    if (Subtarget.isISA3_0()) {
+        if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
+            SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
+            SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
+            SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
+          BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
+            .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
+          break;
+        }
+    }
+
     // We need to move the CR field that contains the CR bit we are spilling.
     // The super register may not be explicitly defined (i.e. it can be defined
     // by a CR-logical that only defines the subreg) so we state that the CR


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