[PATCH] D68360: PR41162 Implement LKK remainder and divisibility algorithms

[Tim Gymnich via Phabricator via llvm-commits]

TG908 created this revision.
TG908 added reviewers: STL_MSFT, MatzeB, kparzysz, efriedma, craig.topper, foad, RKSimon, javed.absar, lebedev.ri, gnudles, hermord, jdoerfert, spatel, xbolva00, dexonsmith, kristina, nikic, nickdesaulniers, majnemer.
TG908 added a project: LLVM.
Herald added subscribers: llvm-commits, jsji, MaskRay, hiraditya, nemanjai.

This patch implements the LLK algorithm for optimizing remainder computations with a constant divisor.
LLK is an improvement on the previously used Granlund-Montgomery-Warren approach.

PR41162 <https://bugs.llvm.org/show_bug.cgi?id=41162>
LLK Paper <https://arxiv.org/pdf/1902.01961.pdf>

**Notes:**

- I added functions `foldSREM` and `foldUREM` in `DAGCombiner.cpp` to handle signed and unsigned remainders.
- Tests have been performed on x86 for every 8 bit signed and unsigned remainder operation.
- Tests for 32 bit signed remainders have been performed on a large set of random integers.
- I also added some llc code gen tests.
- I am a bit unsure whether my `isOperationLegalOrCustomOrPromote` checks are too strict.


Repository:
  rL LLVM

https://reviews.llvm.org/D68360

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/srem-llk.ll
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/AArch64/srem-vector-llk.ll
  llvm/test/CodeGen/AArch64/urem-llk.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/AArch64/urem-vector-llk.ll
  llvm/test/CodeGen/PowerPC/machine-pre.ll
  llvm/test/CodeGen/X86/load-scalar-as-vector.ll
  llvm/test/CodeGen/X86/pr14088.ll
  llvm/test/CodeGen/X86/srem-llk.ll
  llvm/test/CodeGen/X86/srem-vector-llk.ll
  llvm/test/CodeGen/X86/urem-i8-constant.ll
  llvm/test/CodeGen/X86/urem-llk.ll
  llvm/test/CodeGen/X86/urem-vector-llk.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll

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