[PATCH] D68311: [X86] Rewrite to the vXi1 subvector insertion code to not rely on the value of bits that might be undef

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL373495: [X86] Rewrite to the vXi1 subvector insertion code to not rely on the value of… (authored by ctopper, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D68311?vs=222866&id=222873#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68311/new/

https://reviews.llvm.org/D68311

Files:
  llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
  llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll
  llvm/trunk/test/CodeGen/X86/avx512-ext.ll
  llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
  llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
  llvm/trunk/test/CodeGen/X86/masked_store.ll
  llvm/trunk/test/CodeGen/X86/vec_smulo.ll
  llvm/trunk/test/CodeGen/X86/vec_umulo.ll

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