[PATCH] D67950: [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

[Jinsong Ji via Phabricator via llvm-commits]

jsji added inline comments.


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Comment at: llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll:23
 ; CHECK-LE-NEXT:    sxtah r1, r1, lr
+; CHECK-LE-NEXT:    subs r0, #1
 ; CHECK-LE-NEXT:    smlad r12, r4, lr, r12
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Do these changes in scheduling means `ParallelDSP ` SchedModel has some interference with others?
If so, maybe we need another patch to fix that. 


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  https://reviews.llvm.org/D67950/new/

https://reviews.llvm.org/D67950