[PATCH] D68200: [AMDGPU] Extend buffer intrinsics with swizzling

[Piotr Sobczak via Phabricator via llvm-commits]

piotr updated this revision to Diff 222779.
piotr added a comment.

Addressed review comments and rebased.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68200/new/

https://reviews.llvm.org/D68200

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/BUFInstructions.td
  lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
  test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
  test/CodeGen/AMDGPU/clamp-omod-special-case.mir
  test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
  test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
  test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
  test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
  test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
  test/CodeGen/AMDGPU/collapse-endcf.mir
  test/CodeGen/AMDGPU/collapse-endcf2.mir
  test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
  test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
  test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  test/CodeGen/AMDGPU/fold-fi-mubuf.mir
  test/CodeGen/AMDGPU/fold-imm-copy.mir
  test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
  test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
  test/CodeGen/AMDGPU/fold-multiple.mir
  test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
  test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
  test/CodeGen/AMDGPU/indirect-addressing-term.ll
  test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir
  test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
  test/CodeGen/AMDGPU/inserted-wait-states.mir
  test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
  test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
  test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
  test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
  test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
  test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
  test/CodeGen/AMDGPU/memory_clause.mir
  test/CodeGen/AMDGPU/merge-load-store.mir
  test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
  test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
  test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
  test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
  test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
  test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
  test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
  test/CodeGen/AMDGPU/regcoalesce-dbg.mir
  test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
  test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
  test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  test/CodeGen/AMDGPU/schedule-barrier.mir
  test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
  test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
  test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
  test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
  test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
  test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
  test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
  test/CodeGen/MIR/AMDGPU/load-store-opt-dlc.mir
  test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
  test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
  test/CodeGen/MIR/AMDGPU/target-index-operands.mir

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