[PATCH] D68247: [X86] Add a DAG combine to shrink vXi64 gather/scatter indices that are constant with sufficient sign bits to fit in vXi32

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:42384
+  if (DCI.isBeforeLegalize()) {
+    if (auto *BV = dyn_cast<BuildVectorSDNode>(Index)) {
+      unsigned IndexWidth = Index.getScalarValueSizeInBits();
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craig.topper wrote:
> RKSimon wrote:
> > Does it have to be build vector? General truncations should be pretty good in these cases whatever.
> No. I guess you could truncate anytime the index element is wider than the data element and the index type isn't legal and is a type that needs to be split or a type that will be widened to a type that will be split. You wouldn't want to truncate if it won't prevent a split since you'd just be adding more code. Unless it was sext/zext which would be removed, but that's already handled below. Is that what you were thinking?
I was thinking more in terms of the high number of sign bits means that we can always cheaply truncate with VTRUNC/PACKSS


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  https://reviews.llvm.org/D68247/new/

https://reviews.llvm.org/D68247