[PATCH] D68247: [X86] Add a DAG combine to shrink vXi64 gather/scatter indices that are constant with sufficient sign bits to fit in vXi32
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 06:33:56 PDT 2019
RKSimon added inline comments.
================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:42384
+ if (DCI.isBeforeLegalize()) {
+ if (auto *BV = dyn_cast<BuildVectorSDNode>(Index)) {
+ unsigned IndexWidth = Index.getScalarValueSizeInBits();
----------------
Does it have to be build vector? General truncations should be pretty good in these cases whatever.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D68247/new/
https://reviews.llvm.org/D68247
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