[PATCH] D68250: [DAGCombine] Match more patterns for half word bswap

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

vector tests?



================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5773
+  if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
+    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    if (!C || C->getZExtValue() != 16)
----------------
Vector support by using isConstOrConstSplat ?


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5774
+    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    if (!C || C->getZExtValue() != 16)
+      return false;
----------------
!C || C->getAPIntValue() != 16 (helps avoid fuzz test failures)


Repository:
  rL LLVM

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  https://reviews.llvm.org/D68250/new/

https://reviews.llvm.org/D68250