[PATCH] D68264: [AMDGPU] Add VerifyScheduling support.
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 02:58:33 PDT 2019
foad created this revision.
foad added reviewers: arsenm, atrick, tstellar, vpykhtin.
Herald added subscribers: javed.absar, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, MatzeB.
Herald added a project: LLVM.
This is cut and pasted from the corresponding GenericScheduler
functions.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D68264
Files:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Index: llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -196,6 +196,15 @@
assert(BotCand.Reason != NoCand && "failed to find the first candidate");
} else {
LLVM_DEBUG(traceCandidate(BotCand));
+#ifndef NDEBUG
+ if (VerifyScheduling) {
+ SchedCandidate TCand;
+ TCand.reset(CandPolicy());
+ pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), TCand);
+ assert(TCand.SU == BotCand.SU &&
+ "Last pick result should correspond to re-picking right now");
+ }
+#endif
}
// Check if the top Q has a better candidate.
@@ -207,6 +216,15 @@
assert(TopCand.Reason != NoCand && "failed to find the first candidate");
} else {
LLVM_DEBUG(traceCandidate(TopCand));
+#ifndef NDEBUG
+ if (VerifyScheduling) {
+ SchedCandidate TCand;
+ TCand.reset(CandPolicy());
+ pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TCand);
+ assert(TCand.SU == TopCand.SU &&
+ "Last pick result should correspond to re-picking right now");
+ }
+#endif
}
// Pick best from BotCand and TopCand.
Index: llvm/lib/CodeGen/MachineScheduler.cpp
===================================================================
--- llvm/lib/CodeGen/MachineScheduler.cpp
+++ llvm/lib/CodeGen/MachineScheduler.cpp
@@ -82,6 +82,10 @@
DumpCriticalPathLength("misched-dcpl", cl::Hidden,
cl::desc("Print critical path length to stdout"));
+cl::opt<bool> VerifyScheduling(
+ "verify-misched", cl::Hidden,
+ cl::desc("Verify machine instrs before and after machine scheduling"));
+
} // end namespace llvm
#ifndef NDEBUG
@@ -122,9 +126,6 @@
cl::desc("Enable memop clustering."),
cl::init(true));
-static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
- cl::desc("Verify machine instrs before and after machine scheduling"));
-
// DAG subtrees must have at least this many nodes.
static const unsigned MinSubtreeSize = 8;
Index: llvm/include/llvm/CodeGen/MachineScheduler.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineScheduler.h
+++ llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -100,6 +100,7 @@
extern cl::opt<bool> ForceTopDown;
extern cl::opt<bool> ForceBottomUp;
+extern cl::opt<bool> VerifyScheduling;
class LiveIntervals;
class MachineDominatorTree;
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