[llvm] r373269 - [DAGCombiner] Clang format MatchRotate. NFC
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 30 14:41:52 PDT 2019
Author: deadalnix
Date: Mon Sep 30 14:41:52 2019
New Revision: 373269
URL: http://llvm.org/viewvc/llvm-project?rev=373269&view=rev
Log:
[DAGCombiner] Clang format MatchRotate. NFC
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=373269&r1=373268&r2=373269&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Sep 30 14:41:52 2019
@@ -6375,12 +6375,14 @@ SDValue DAGCombiner::MatchRotatePosNeg(S
SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
// Must be a legal type. Expanded 'n promoted things won't work with rotates.
EVT VT = LHS.getValueType();
- if (!TLI.isTypeLegal(VT)) return SDValue();
+ if (!TLI.isTypeLegal(VT))
+ return SDValue();
// The target must have at least one rotate flavor.
bool HasROTL = hasOperation(ISD::ROTL, VT);
bool HasROTR = hasOperation(ISD::ROTR, VT);
- if (!HasROTL && !HasROTR) return SDValue();
+ if (!HasROTL && !HasROTR)
+ return SDValue();
// Check for truncated rotate.
if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
@@ -6430,10 +6432,10 @@ SDValue DAGCombiner::MatchRotate(SDValue
// At this point we've matched or extracted a shift op on each side.
if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
- return SDValue(); // Not shifting the same value.
+ return SDValue(); // Not shifting the same value.
if (LHSShift.getOpcode() == RHSShift.getOpcode())
- return SDValue(); // Shifts must disagree.
+ return SDValue(); // Shifts must disagree.
// Canonicalize shl to left side in a shl/srl pair.
if (RHSShift.getOpcode() == ISD::SHL) {
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