[PATCH] D68167: [X86] Add a DAG combine to transform (add (zext (vXi1 X)), Y) -> (sub Y, (sext (vXi1 X))) with avx512

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

This is already in trunk with:
rL373136 <https://reviews.llvm.org/rL373136>
...so call this post-commit review? :)

Instead of checking for AVX512, would it be better to check that the bool vector type is actually legal as the code comment specifies? Eg:

  TLI.isTypeLegal(Op0.getOperand(0).getValueType())


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68167/new/

https://reviews.llvm.org/D68167