[PATCH] D68098: [AArch64][SVE] Adding patterns for floating point SVE add instructions.

[Graham Hunter via Phabricator via llvm-commits]

huntergr accepted this revision.
huntergr added a comment.
This revision is now accepted and ready to land.

LGTM.

You can add the extra multiclass for `ftsmul` if you wish, but it's not needed until someone implements a matching pattern for that instruction. We only match it against an ACLE intrinsic downstream, not common SDag nodes.



================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1218
+                      ZPRRegOp zprty,
+                      ValueType vt, ValueType vt2, SDPatternOperator op>
 : I<(outs zprty:$Zd), (ins  zprty:$Zn, zprty:$Zm),
----------------
amehsan wrote:
> Just realized that I forgot to check if we really need two distinct ValueType here or not. I will check that and remove it if not needed.
I guess I left a bit out; the reason for the second valuetype was for the `ftsmul` instruction, which takes a vector of integers as one of the arguments.  We added a second multiclass just for that instruction:

```
multiclass sve_fp_3op_u_zd_ftsmul<bits<3> opc, string asm,
                                  SDPatternOperator op> {
  def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16, nxv8f16, nxv8i16, op>;
  def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32, nxv4f32, nxv4i32, op>;
  def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64, nxv2f64, nxv2i64, op>;
}
```


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