[PATCH] D68203: [SelectionDAG][SVE] Add ISD node for VSCALE.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: rengolin, cameron.mcinally, hfinkel, sebpop, SjoerdMeijer.
Herald added subscribers: psnobl, tschuett.

To represent `vscale` in ISel we need to have a dedicated node that
can be legalized to one or more instructions to materialize the runtime
vector length.

This patch defines the node ISD::VSCALE of type integer, which takes a
single immediate. The immediate is a multiplier for the scale.

This patch also adds SVE CodeGen support for VSCALE, which maps this
node to RDVL instructions (for scaled multiples of 16bytes) or CNT[HSD]
instructions (scaled multiples of 2, 4, or 8 bytes, respectively).


https://reviews.llvm.org/D68203

Files:
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/CodeGen/SelectionDAG.h
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.h
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/AArch64/AArch64SVEInstrInfo.td
  test/CodeGen/AArch64/sve-vscale.ll

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