[PATCH] D68121: [X86] Model MXCSR for all SSE instructions

[Pengfei Wang via Phabricator via llvm-commits]

pengfei marked an inline comment as done.
pengfei added inline comments.


================
Comment at: llvm/test/CodeGen/X86/evex-to-vex-compress.mir:2317
   $xmm0 = VMOVZPQILo2PQIZrr                    $xmm0                                                   
-  ; CHECK: VCOMISDrm_Int                       $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VCOMISDZrm_Int                               $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VCOMISDrr_Int                       $xmm0, $xmm1, implicit-def $eflags  
-  VCOMISDZrr_Int                               $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VCOMISSrm_Int                       $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VCOMISSZrm_Int                               $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VCOMISSrr_Int                       $xmm0, $xmm1, implicit-def $eflags 
-  VCOMISSZrr_Int                               $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VUCOMISDrm_Int                      $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VUCOMISDZrm_Int                              $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VUCOMISDrr_Int                      $xmm0, $xmm1, implicit-def $eflags
-  VUCOMISDZrr_Int                              $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VUCOMISSrm_Int                      $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VUCOMISSZrm_Int                              $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VUCOMISSrr_Int                      $xmm0, $xmm1, implicit-def $eflags 
-  VUCOMISSZrr_Int                              $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VCOMISDrm                           $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VCOMISDZrm                                   $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VCOMISDrr                           $xmm0, $xmm1, implicit-def $eflags 
-  VCOMISDZrr                                   $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VCOMISSrm                           $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VCOMISSZrm                                   $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VCOMISSrr                           $xmm0, $xmm1, implicit-def $eflags 
-  VCOMISSZrr                                   $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VUCOMISDrm                          $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VUCOMISDZrm                                  $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VUCOMISDrr                          $xmm0, $xmm1, implicit-def $eflags 
-  VUCOMISDZrr                                  $xmm0, $xmm1, implicit-def $eflags                      
-  ; CHECK: VUCOMISSrm                          $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  VUCOMISSZrm                                  $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags
-  ; CHECK: VUCOMISSrr                          $xmm0, $xmm1, implicit-def $eflags 
-  VUCOMISSZrr                                  $xmm0, $xmm1, implicit-def $eflags 
+  ; CHECK: VCOMISDrm_Int                       $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
+  VCOMISDZrm_Int                               $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
----------------
craig.topper wrote:
> Why are only COMI instructions updated?
We don't have any special test case for checking the operands of MIs, and I checked other target don't either. This file may be the one that checks most AVX/AVX512 MIs, but we only modeled SSE instructions in this patch. 
VCOMI shouldn't be updated either. The reason is VCOMISS/VCOMISD are defined is X86InstrSSE.td and using sse12_ord_cmp which I modeled MXCSR in.
In fact, I just made sure all SSE instructions are correctly modeled, not all modeled instructions are SSE. I think it doesn't matter, because it is NFC and we will model AVX instructions next.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68121/new/

https://reviews.llvm.org/D68121