[PATCH] D67981: [NFC][PowerPC] Adding FeatureFPU in the definition of FeatureISA3_0

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPC.td:193
+                                     "Enable instructions added in ISA 3.0.",
+                                     [FeatureFPU]>;
 def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
----------------
jsji wrote:
> jsji wrote:
> > Looks like there is some misunderstanding of what `FeatureISA3_0` is for?
> > 
> > As in the description, `FeatureISA3_0` is for new instruction added in ISA 3.0, not all the instructions in ISA 3.0.
> > Why it need to depend on FeatureFPU?
> > 
> > In other words, with the new patch `-mattr=-fpu` will also remove `isa-v30-instructions` effectively.
> > So that means, if you add -mattr=-fpu, you can't use any of the new instruction added for P8? 
> > Is that what you intended?
> > 
> I meant `P9`.
Yes. That is very much part of the intent here. It is not possible to have a CPU that conforms to ISA 3.0 that does not support HW floating point operations (i.e. doesn't have a HW FPU).

Having an FPU does not imply we have an implementation of ISA 3.0. But having an implementation of ISA 3.0 **absolutely** implies having an FPU.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67981/new/

https://reviews.llvm.org/D67981