[llvm] r373108 - [X86] Call SimplifyDemandedBits in combineGatherScatter any time the mask element is wider than i1, not just when AVX512 is disabled.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 27 11:23:55 PDT 2019


Author: ctopper
Date: Fri Sep 27 11:23:55 2019
New Revision: 373108

URL: http://llvm.org/viewvc/llvm-project?rev=373108&view=rev
Log:
[X86] Call SimplifyDemandedBits in combineGatherScatter any time the mask element is wider than i1, not just when AVX512 is disabled.

The AVX2 intrinsics can still be used when AVX512 is enabled and
those go through this path. So we should simplify them.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=373108&r1=373107&r2=373108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 27 11:23:55 2019
@@ -43425,10 +43425,10 @@ static SDValue combineGatherScatter(SDNo
     }
   }
 
-  // With AVX2 we only demand the upper bit of the mask.
-  if (!Subtarget.hasAVX512()) {
+  // With vector masks we only demand the upper bit of the mask.
+  SDValue Mask = N->getOperand(2);
+  if (Mask.getScalarValueSizeInBits() != 1) {
     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-    SDValue Mask = N->getOperand(2);
     APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits()));
     if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI))
       return SDValue(N, 0);

Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll?rev=373108&r1=373107&r2=373108&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Fri Sep 27 11:23:55 2019
@@ -2205,7 +2205,6 @@ define <2 x i64> @test_mask_demanded_bit
 ; X86-AVX512VL:       # %bb.0:
 ; X86-AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
 ; X86-AVX512VL-NEXT:    vpsllq $63, %xmm2, %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xe9,0x73,0xf2,0x3f]
-; X86-AVX512VL-NEXT:    vpsraq $63, %xmm2, %xmm2 # encoding: [0x62,0xf1,0xed,0x08,0x72,0xe2,0x3f]
 ; X86-AVX512VL-NEXT:    vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 # encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48]
 ; X86-AVX512VL-NEXT:    retl # encoding: [0xc3]
 ;
@@ -2218,7 +2217,6 @@ define <2 x i64> @test_mask_demanded_bit
 ; X64-AVX512VL-LABEL: test_mask_demanded_bits:
 ; X64-AVX512VL:       # %bb.0:
 ; X64-AVX512VL-NEXT:    vpsllq $63, %xmm2, %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xe9,0x73,0xf2,0x3f]
-; X64-AVX512VL-NEXT:    vpsraq $63, %xmm2, %xmm2 # encoding: [0x62,0xf1,0xed,0x08,0x72,0xe2,0x3f]
 ; X64-AVX512VL-NEXT:    vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x4f]
 ; X64-AVX512VL-NEXT:    retq # encoding: [0xc3]
   %mask1 = sext <2 x i1> %mask to <2 x i64>




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