[llvm] r373040 - [WebAssembly] SIMD Load and extend operations
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 26 19:06:50 PDT 2019
Author: tlively
Date: Thu Sep 26 19:06:50 2019
New Revision: 373040
URL: http://llvm.org/viewvc/llvm-project?rev=373040&view=rev
Log:
[WebAssembly] SIMD Load and extend operations
Summary:
As specified at
https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend.
These instructions are behind the unimplemented-simd128 target feature
for now because they have not been implemented in V8 yet.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68058
Removed:
llvm/trunk/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll
Modified:
llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/trunk/test/CodeGen/WebAssembly/simd-offset.ll
llvm/trunk/test/MC/WebAssembly/simd-encodings.s
Modified: llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h?rev=373040&r1=373039&r2=373040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h Thu Sep 26 19:06:50 2019
@@ -332,6 +332,18 @@ inline unsigned GetDefaultP2AlignAny(uns
case WebAssembly::ATOMIC_WAIT_I64_S:
case WebAssembly::LOAD_SPLAT_v64x2:
case WebAssembly::LOAD_SPLAT_v64x2_S:
+ case WebAssembly::LOAD_EXTEND_S_v8i16:
+ case WebAssembly::LOAD_EXTEND_S_v8i16_S:
+ case WebAssembly::LOAD_EXTEND_U_v8i16:
+ case WebAssembly::LOAD_EXTEND_U_v8i16_S:
+ case WebAssembly::LOAD_EXTEND_S_v4i32:
+ case WebAssembly::LOAD_EXTEND_S_v4i32_S:
+ case WebAssembly::LOAD_EXTEND_U_v4i32:
+ case WebAssembly::LOAD_EXTEND_U_v4i32_S:
+ case WebAssembly::LOAD_EXTEND_S_v2i64:
+ case WebAssembly::LOAD_EXTEND_S_v2i64_S:
+ case WebAssembly::LOAD_EXTEND_U_v2i64:
+ case WebAssembly::LOAD_EXTEND_U_v2i64_S:
return 3;
case WebAssembly::LOAD_V128:
case WebAssembly::LOAD_V128_S:
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=373040&r1=373039&r2=373040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Thu Sep 26 19:06:50 2019
@@ -228,7 +228,7 @@ WebAssemblyTargetLowering::WebAssemblyTa
// - Floating-point extending loads.
// - Floating-point truncating stores.
// - i1 extending loads.
- // - extending/truncating SIMD loads/stores
+ // - truncating SIMD stores and most extending loads
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
for (auto T : MVT::integer_valuetypes())
@@ -245,6 +245,14 @@ WebAssemblyTargetLowering::WebAssemblyTa
}
}
}
+ // But some vector extending loads are legal
+ if (Subtarget->hasUnimplementedSIMD128()) {
+ for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
+ setLoadExtAction(Ext, MVT::v8i16, MVT::v8i8, Legal);
+ setLoadExtAction(Ext, MVT::v4i32, MVT::v4i16, Legal);
+ setLoadExtAction(Ext, MVT::v2i64, MVT::v2i32, Legal);
+ }
+ }
}
// Don't do anything clever with build_pairs
@@ -540,6 +548,16 @@ bool WebAssemblyTargetLowering::isIntDiv
return true;
}
+bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
+ if (!Subtarget->hasUnimplementedSIMD128())
+ return false;
+ MVT ExtT = ExtVal.getSimpleValueType();
+ MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0);
+ return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
+ (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
+ (ExtT == MVT::v2i64 && MemT == MVT::v2i32);
+}
+
EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL,
LLVMContext &C,
EVT VT) const {
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h?rev=373040&r1=373039&r2=373040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h Thu Sep 26 19:06:50 2019
@@ -63,7 +63,7 @@ private:
MachineMemOperand::Flags Flags,
bool *Fast) const override;
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
-
+ bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=373040&r1=373039&r2=373040&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Thu Sep 26 19:06:50 2019
@@ -104,6 +104,45 @@ def : LoadPatGlobalAddrOffOnly<!cast<Val
!cast<NI>("LOAD_SPLAT_"#args[1])>;
}
+// Load and extend
+multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
+ let mayLoad = 1, UseNamedOperandTable = 1,
+ Predicates = [HasUnimplementedSIMD128] in {
+ defm LOAD_EXTEND_S_#vec_t :
+ SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
+ (outs), (ins P2Align:$p2align, offset32_op:$off), [],
+ name#"_s\t$dst, ${off}(${addr})$p2align",
+ name#"_s\t$off$p2align", simdop>;
+ defm LOAD_EXTEND_U_#vec_t :
+ SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
+ (outs), (ins P2Align:$p2align, offset32_op:$off), [],
+ name#"_u\t$dst, ${off}(${addr})$p2align",
+ name#"_u\t$off$p2align", !add(simdop, 1)>;
+ }
+}
+
+defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 210>;
+defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 212>;
+defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 214>;
+
+let Predicates = [HasUnimplementedSIMD128] in
+foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in
+foreach exts = [["sextloadv", "_S"],
+ ["zextloadv", "_U"],
+ ["extloadv", "_U"]] in {
+def : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]),
+ !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
+def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm,
+ !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
+def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add,
+ !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
+def : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
+ !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
+def : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
+ !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
+}
+
+
// Store: v128.store
let mayStore = 1, UseNamedOperandTable = 1 in
defm STORE_V128 :
Removed: llvm/trunk/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll?rev=373039&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll (removed)
@@ -1,57 +0,0 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s
-
-; Check that store in memory with smaller lanes are loaded and stored
-; as expected. This is a regression test for part of bug 39275.
-
-target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
-target triple = "wasm32-unknown-unknown"
-
-; CHECK-LABEL: load_ext_2xi32:
-; CHECK-NEXT: .functype load_ext_2xi32 (i32) -> (v128){{$}}
-; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
-; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
-; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
-; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-define <2 x i32> @load_ext_2xi32(<2 x i32>* %p) {
- %1 = load <2 x i32>, <2 x i32>* %p, align 4
- ret <2 x i32> %1
-}
-
-; CHECK-LABEL: load_zext_2xi32:
-; CHECK-NEXT: .functype load_zext_2xi32 (i32) -> (v128){{$}}
-; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
-; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
-; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
-; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-define <2 x i64> @load_zext_2xi32(<2 x i32>* %p) {
- %1 = load <2 x i32>, <2 x i32>* %p, align 4
- %2 = zext <2 x i32> %1 to <2 x i64>
- ret <2 x i64> %2
-}
-
-; CHECK-LABEL: load_sext_2xi32:
-; CHECK-NEXT: .functype load_sext_2xi32 (i32) -> (v128){{$}}
-; CHECK-NEXT: i64.load32_s $push[[L0:[0-9]+]]=, 0($0){{$}}
-; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
-; CHECK-NEXT: i64.load32_s $push[[L2:[0-9]+]]=, 4($0){{$}}
-; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-define <2 x i64> @load_sext_2xi32(<2 x i32>* %p) {
- %1 = load <2 x i32>, <2 x i32>* %p, align 4
- %2 = sext <2 x i32> %1 to <2 x i64>
- ret <2 x i64> %2
-}
-
-; CHECK-LABEL: store_trunc_2xi32:
-; CHECK-NEXT: .functype store_trunc_2xi32 (i32, v128) -> (){{$}}
-; CHECK-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $1, 1
-; CHECK-NEXT: i64.store32 4($0), $pop[[L0]]
-; CHECK-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0
-; CHECK-NEXT: i64.store32 0($0), $pop[[L1]]
-; CHECK-NEXT: return
-define void @store_trunc_2xi32(<2 x i32>* %p, <2 x i32> %x) {
- store <2 x i32> %x, <2 x i32>* %p, align 4
- ret void
-}
Modified: llvm/trunk/test/CodeGen/WebAssembly/simd-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-offset.ll?rev=373040&r1=373039&r2=373040&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-offset.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-offset.ll Thu Sep 26 19:06:50 2019
@@ -338,6 +338,38 @@ define <8 x i16> @load_splat_v8i16(i16*
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_sext_v8i16(<8 x i8>* %p) {
+ %v = load <8 x i8>, <8 x i8>* %p
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16(<8 x i8>* %p) {
+ %v = load <8 x i8>, <8 x i8>* %p
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16(<8 x i8>* %p) {
+ %v = load <8 x i8>, <8 x i8>* %p
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_with_folded_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_with_folded_offset (i32) -> (v128){{$}}
@@ -366,6 +398,47 @@ define <8 x i16> @load_splat_v8i16_with_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_sext_v8i16_with_folded_offset(<8 x i8>* %p) {
+ %q = ptrtoint <8 x i8>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16_with_folded_offset(<8 x i8>* %p) {
+ %q = ptrtoint <8 x i8>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_with_folded_offset:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16_with_folded_offset(<8 x i8>* %p) {
+ %q = ptrtoint <8 x i8>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_with_folded_gep_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
@@ -390,6 +463,41 @@ define <8 x i16> @load_splat_v8i16_with_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_sext_v8i16_with_folded_gep_offset(<8 x i8>* %p) {
+ %s = getelementptr inbounds <8 x i8>, <8 x i8>* %p, i32 1
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16_with_folded_gep_offset(<8 x i8>* %p) {
+ %s = getelementptr inbounds <8 x i8>, <8 x i8>* %p, i32 1
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_with_folded_gep_offset:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16_with_folded_gep_offset(<8 x i8>* %p) {
+ %s = getelementptr inbounds <8 x i8>, <8 x i8>* %p, i32 1
+ %v = load <8 x i8>, <8 x i8>* %s
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_with_unfolded_gep_negative_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
@@ -418,6 +526,47 @@ define <8 x i16> @load_splat_v8i16_with_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_sext_v8i16_with_unfolded_gep_negative_offset(<8 x i8>* %p) {
+ %s = getelementptr inbounds <8 x i8>, <8 x i8>* %p, i32 -1
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16_with_unfolded_gep_negative_offset(<8 x i8>* %p) {
+ %s = getelementptr inbounds <8 x i8>, <8 x i8>* %p, i32 -1
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16_with_unfolded_gep_negative_offset(<8 x i8>* %p) {
+ %s = getelementptr inbounds <8 x i8>, <8 x i8>* %p, i32 -1
+ %v = load <8 x i8>, <8 x i8>* %s
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_with_unfolded_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
@@ -450,6 +599,53 @@ define <8 x i16> @load_splat_v8i16_with_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[L0:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[L0]]{{$}}
+define <8 x i16> @load_sext_v8i16_with_unfolded_offset(<8 x i8>* %p) {
+ %q = ptrtoint <8 x i8>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[L0:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[L0]]{{$}}
+define <8 x i16> @load_zext_v8i16_with_unfolded_offset(<8 x i8>* %p) {
+ %q = ptrtoint <8 x i8>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_with_unfolded_offset:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[L0:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[L0]]{{$}}
+define <8 x i8> @load_ext_v8i16_with_unfolded_offset(<8 x i8>* %p) {
+ %q = ptrtoint <8 x i8>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_with_unfolded_gep_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
@@ -478,6 +674,47 @@ define <8 x i16> @load_splat_v8i16_with_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_sext_v8i16_with_unfolded_gep_offset(<8 x i8>* %p) {
+ %s = getelementptr <8 x i8>, <8 x i8>* %p, i32 1
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16_with_unfolded_gep_offset(<8 x i8>* %p) {
+ %s = getelementptr <8 x i8>, <8 x i8>* %p, i32 1
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16_with_unfolded_gep_offset(<8 x i8>* %p) {
+ %s = getelementptr <8 x i8>, <8 x i8>* %p, i32 1
+ %v = load <8 x i8>, <8 x i8>* %s
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_from_numeric_address:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_from_numeric_address () -> (v128){{$}}
@@ -504,6 +741,44 @@ define <8 x i16> @load_splat_v8i16_from_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_sext_v8i16_from_numeric_address() {
+ %s = inttoptr i32 32 to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16_from_numeric_address() {
+ %s = inttoptr i32 32 to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_from_numeric_address:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16_from_numeric_address() {
+ %s = inttoptr i32 32 to <8 x i8>*
+ %v = load <8 x i8>, <8 x i8>* %s
+ ret <8 x i8> %v
+}
+
; CHECK-LABEL: load_v8i16_from_global_address:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v8i16_from_global_address () -> (v128){{$}}
@@ -530,6 +805,43 @@ define <8 x i16> @load_splat_v8i16_from_
ret <8 x i16> %v2
}
+; CHECK-LABEL: load_sext_v8i16_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v8i16_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i16x8.load8x8_s $push[[R:[0-9]+]]=, gv_v8i8($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+ at gv_v8i8 = global <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
+define <8 x i16> @load_sext_v8i16_from_global_address() {
+ %v = load <8 x i8>, <8 x i8>* @gv_v8i8
+ %v2 = sext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_zext_v8i16_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v8i16_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, gv_v8i8($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i16> @load_zext_v8i16_from_global_address() {
+ %v = load <8 x i8>, <8 x i8>* @gv_v8i8
+ %v2 = zext <8 x i8> %v to <8 x i16>
+ ret <8 x i16> %v2
+}
+
+; CHECK-LABEL: load_ext_v8i16_from_global_address:
+; NO-SIMD128-NOT: load8x8
+; SIMD128-NEXT: .functype load_ext_v8i16_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i16x8.load8x8_u $push[[R:[0-9]+]]=, gv_v8i8($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <8 x i8> @load_ext_v8i16_from_global_address() {
+ %v = load <8 x i8>, <8 x i8>* @gv_v8i8
+ ret <8 x i8> %v
+}
+
+
; CHECK-LABEL: store_v8i16:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype store_v8i16 (v128, i32) -> (){{$}}
@@ -642,6 +954,38 @@ define <4 x i32> @load_splat_v4i32(i32*
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32(<4 x i16>* %p) {
+ %v = load <4 x i16>, <4 x i16>* %p
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32(<4 x i16>* %p) {
+ %v = load <4 x i16>, <4 x i16>* %p
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32(<4 x i16>* %p) {
+ %v = load <4 x i16>, <4 x i16>* %p
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_with_folded_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_with_folded_offset (i32) -> (v128){{$}}
@@ -670,6 +1014,47 @@ define <4 x i32> @load_splat_v4i32_with_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32_with_folded_offset(<4 x i16>* %p) {
+ %q = ptrtoint <4 x i16>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_with_folded_offset(<4 x i16>* %p) {
+ %q = ptrtoint <4 x i16>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_with_folded_offset:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_with_folded_offset(<4 x i16>* %p) {
+ %q = ptrtoint <4 x i16>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_with_folded_gep_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
@@ -694,6 +1079,41 @@ define <4 x i32> @load_splat_v4i32_with_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32_with_folded_gep_offset(<4 x i16>* %p) {
+ %s = getelementptr inbounds <4 x i16>, <4 x i16>* %p, i32 1
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_with_folded_gep_offset(<4 x i16>* %p) {
+ %s = getelementptr inbounds <4 x i16>, <4 x i16>* %p, i32 1
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_with_folded_gep_offset:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_with_folded_gep_offset(<4 x i16>* %p) {
+ %s = getelementptr inbounds <4 x i16>, <4 x i16>* %p, i32 1
+ %v = load <4 x i16>, <4 x i16>* %s
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_with_unfolded_gep_negative_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
@@ -722,6 +1142,47 @@ define <4 x i32> @load_splat_v4i32_with_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32_with_unfolded_gep_negative_offset(<4 x i16>* %p) {
+ %s = getelementptr inbounds <4 x i16>, <4 x i16>* %p, i32 -1
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_with_unfolded_gep_negative_offset(<4 x i16>* %p) {
+ %s = getelementptr inbounds <4 x i16>, <4 x i16>* %p, i32 -1
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_with_unfolded_gep_negative_offset(<4 x i16>* %p) {
+ %s = getelementptr inbounds <4 x i16>, <4 x i16>* %p, i32 -1
+ %v = load <4 x i16>, <4 x i16>* %s
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_with_unfolded_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
@@ -754,6 +1215,53 @@ define <4 x i32> @load_splat_v4i32_with_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32_with_unfolded_offset(<4 x i16>* %p) {
+ %q = ptrtoint <4 x i16>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_with_unfolded_offset(<4 x i16>* %p) {
+ %q = ptrtoint <4 x i16>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_with_unfolded_offset:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_with_unfolded_offset(<4 x i16>* %p) {
+ %q = ptrtoint <4 x i16>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_with_unfolded_gep_offset:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
@@ -782,6 +1290,47 @@ define <4 x i32> @load_splat_v4i32_with_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32_with_unfolded_gep_offset(<4 x i16>* %p) {
+ %s = getelementptr <4 x i16>, <4 x i16>* %p, i32 1
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_with_unfolded_gep_offset(<4 x i16>* %p) {
+ %s = getelementptr <4 x i16>, <4 x i16>* %p, i32 1
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_with_unfolded_gep_offset(<4 x i16>* %p) {
+ %s = getelementptr <4 x i16>, <4 x i16>* %p, i32 1
+ %v = load <4 x i16>, <4 x i16>* %s
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_from_numeric_address:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_from_numeric_address () -> (v128){{$}}
@@ -808,6 +1357,44 @@ define <4 x i32> @load_splat_v4i32_from_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_sext_v4i32_from_numeric_address() {
+ %s = inttoptr i32 32 to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_from_numeric_address() {
+ %s = inttoptr i32 32 to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_from_numeric_address:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_from_numeric_address() {
+ %s = inttoptr i32 32 to <4 x i16>*
+ %v = load <4 x i16>, <4 x i16>* %s
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: load_v4i32_from_global_address:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype load_v4i32_from_global_address () -> (v128){{$}}
@@ -834,6 +1421,42 @@ define <4 x i32> @load_splat_v4i32_from_
ret <4 x i32> %v2
}
+; CHECK-LABEL: load_sext_v4i32_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v4i32_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i32x4.load16x4_s $push[[R:[0-9]+]]=, gv_v4i16($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+ at gv_v4i16 = global <4 x i16> <i16 42, i16 42, i16 42, i16 42>
+define <4 x i32> @load_sext_v4i32_from_global_address() {
+ %v = load <4 x i16>, <4 x i16>* @gv_v4i16
+ %v2 = sext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_zext_v4i32_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v4i32_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, gv_v4i16($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i32> @load_zext_v4i32_from_global_address() {
+ %v = load <4 x i16>, <4 x i16>* @gv_v4i16
+ %v2 = zext <4 x i16> %v to <4 x i32>
+ ret <4 x i32> %v2
+}
+
+; CHECK-LABEL: load_ext_v4i32_from_global_address:
+; NO-SIMD128-NOT: load16x4
+; SIMD128-NEXT: .functype load_ext_v4i32_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i32x4.load16x4_u $push[[R:[0-9]+]]=, gv_v4i16($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x i16> @load_ext_v4i32_from_global_address() {
+ %v = load <4 x i16>, <4 x i16>* @gv_v4i16
+ ret <4 x i16> %v
+}
+
; CHECK-LABEL: store_v4i32:
; NO-SIMD128-NOT: v128
; SIMD128-NEXT: .functype store_v4i32 (v128, i32) -> (){{$}}
@@ -949,6 +1572,41 @@ define <2 x i64> @load_splat_v2i64(i64*
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64(<2 x i32>* %p) {
+ %v = load <2 x i32>, <2 x i32>* %p
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64(<2 x i32>* %p) {
+ %v = load <2 x i32>, <2 x i32>* %p
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64 (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64(<2 x i32>* %p) {
+ %v = load <2 x i32>, <2 x i32>* %p
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_with_folded_offset:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -979,6 +1637,50 @@ define <2 x i64> @load_splat_v2i64_with_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64_with_folded_offset(<2 x i32>* %p) {
+ %q = ptrtoint <2 x i32>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_with_folded_offset(<2 x i32>* %p) {
+ %q = ptrtoint <2 x i32>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_with_folded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_with_folded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 16($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_with_folded_offset(<2 x i32>* %p) {
+ %q = ptrtoint <2 x i32>* %p to i32
+ %r = add nuw i32 %q, 16
+ %s = inttoptr i32 %r to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_with_folded_gep_offset:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -1005,6 +1707,44 @@ define <2 x i64> @load_splat_v2i64_with_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64_with_folded_gep_offset(<2 x i32>* %p) {
+ %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 1
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_with_folded_gep_offset(<2 x i32>* %p) {
+ %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 1
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_with_folded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 8($0){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_with_folded_gep_offset(<2 x i32>* %p) {
+ %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 1
+ %v = load <2 x i32>, <2 x i32>* %s
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_with_unfolded_gep_negative_offset:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -1035,6 +1775,50 @@ define <2 x i64> @load_splat_v2i64_with_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64_with_unfolded_gep_negative_offset(<2 x i32>* %p) {
+ %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 -1
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_with_unfolded_gep_negative_offset(<2 x i32>* %p) {
+ %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 -1
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_with_unfolded_gep_negative_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_with_unfolded_gep_negative_offset(<2 x i32>* %p) {
+ %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 -1
+ %v = load <2 x i32>, <2 x i32>* %s
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_with_unfolded_offset:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -1069,6 +1853,56 @@ define <2 x i64> @load_splat_v2i64_with_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64_with_unfolded_offset(<2 x i32>* %p) {
+ %q = ptrtoint <2 x i32>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_with_unfolded_offset(<2 x i32>* %p) {
+ %q = ptrtoint <2 x i32>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_with_unfolded_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_with_unfolded_offset(<2 x i32>* %p) {
+ %q = ptrtoint <2 x i32>* %p to i32
+ %r = add nsw i32 %q, 16
+ %s = inttoptr i32 %r to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_with_unfolded_gep_offset:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -1099,6 +1933,50 @@ define <2 x i64> @load_splat_v2i64_with_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64_with_unfolded_gep_offset(<2 x i32>* %p) {
+ %s = getelementptr <2 x i32>, <2 x i32>* %p, i32 1
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_with_unfolded_gep_offset(<2 x i32>* %p) {
+ %s = getelementptr <2 x i32>, <2 x i32>* %p, i32 1
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_with_unfolded_gep_offset:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
+; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_with_unfolded_gep_offset(<2 x i32>* %p) {
+ %s = getelementptr <2 x i32>, <2 x i32>* %p, i32 1
+ %v = load <2 x i32>, <2 x i32>* %s
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_from_numeric_address:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -1127,6 +2005,47 @@ define <2 x i64> @load_splat_v2i64_from_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_sext_v2i64_from_numeric_address() {
+ %s = inttoptr i32 32 to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_from_numeric_address() {
+ %s = inttoptr i32 32 to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_from_numeric_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_from_numeric_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_from_numeric_address() {
+ %s = inttoptr i32 32 to <2 x i32>*
+ %v = load <2 x i32>, <2 x i32>* %s
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: load_v2i64_from_global_address:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
@@ -1155,6 +2074,45 @@ define <2 x i64> @load_splat_v2i64_from_
ret <2 x i64> %v2
}
+; CHECK-LABEL: load_sext_v2i64_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_sext_v2i64_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+ at gv_v2i32 = global <2 x i32> <i32 42, i32 42>
+define <2 x i64> @load_sext_v2i64_from_global_address() {
+ %v = load <2 x i32>, <2 x i32>* @gv_v2i32
+ %v2 = sext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_zext_v2i64_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: v128
+; SIMD128-NEXT: .functype load_zext_v2i64_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @load_zext_v2i64_from_global_address() {
+ %v = load <2 x i32>, <2 x i32>* @gv_v2i32
+ %v2 = zext <2 x i32> %v to <2 x i64>
+ ret <2 x i64> %v2
+}
+
+; CHECK-LABEL: load_ext_v2i64_from_global_address:
+; NO-SIMD128-NOT: v128
+; SIMD128-VM-NOT: load32x2
+; SIMD128-NEXT: .functype load_ext_v2i64_from_global_address () -> (v128){{$}}
+; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
+; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i32> @load_ext_v2i64_from_global_address() {
+ %v = load <2 x i32>, <2 x i32>* @gv_v2i32
+ ret <2 x i32> %v
+}
+
; CHECK-LABEL: store_v2i64:
; NO-SIMD128-NOT: v128
; SIMD128-VM-NOT: v128
Modified: llvm/trunk/test/MC/WebAssembly/simd-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/WebAssembly/simd-encodings.s?rev=373040&r1=373039&r2=373040&view=diff
==============================================================================
--- llvm/trunk/test/MC/WebAssembly/simd-encodings.s (original)
+++ llvm/trunk/test/MC/WebAssembly/simd-encodings.s Thu Sep 26 19:06:50 2019
@@ -511,4 +511,22 @@ main:
# CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xd1,0x01]
i32x4.widen_high_i16x8_u
+ # CHECK: i16x8.load8x8_s 32 # encoding: [0xfd,0xd2,0x01,0x03,0x20]
+ i16x8.load8x8_s 32
+
+ # CHECK: i16x8.load8x8_u 32 # encoding: [0xfd,0xd3,0x01,0x03,0x20]
+ i16x8.load8x8_u 32
+
+ # CHECK: i32x4.load16x4_s 32 # encoding: [0xfd,0xd4,0x01,0x03,0x20]
+ i32x4.load16x4_s 32
+
+ # CHECK: i32x4.load16x4_u 32 # encoding: [0xfd,0xd5,0x01,0x03,0x20]
+ i32x4.load16x4_u 32
+
+ # CHECK: i64x2.load32x2_s 32 # encoding: [0xfd,0xd6,0x01,0x03,0x20]
+ i64x2.load32x2_s 32
+
+ # CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0xd7,0x01,0x03,0x20]
+ i64x2.load32x2_u 32
+
end_function
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