[PATCH] D68060: [RISCV] Materialization of 64-bit mask immediate
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 25 15:55:44 PDT 2019
luismarques created this revision.
luismarques added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
This approach of materializing 64-bit masks using ADDI+SRLI was suggested a while ago by @lewis-revill [1] but never implemented.
- The `ShiftAmount` is tweaked;
- In the code generated for the expansion of `fcopysign(a, -b)` an addi was replaced by a srli. This could be slightly slower (e.g. picorv32) but it's probably not very concerning. Even the E31 has single-cycle shifts, and these softfloat computations are probably not important workloads for microcontrollers.
[1] https://reviews.llvm.org/D52961?id=169524#inline-470319
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D68060
Files:
llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
llvm/test/CodeGen/RISCV/imm.ll
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