[PATCH] D68025: [MC][ARM] vscclrm disassembles as vldmia

[Alexandros Lamprineas via Phabricator via llvm-commits]

labrinea created this revision.
labrinea added reviewers: ostannard, miyuki, chill.
labrinea added a project: LLVM.
Herald added subscribers: dmgreen, hiraditya, kristof.beyls.

Happens only when the `mve.fp` subtarget feature is enabled:

  $ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
  	.text
  	vldmia	pc, {d0, d1, d2, d3}
  $ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
  	.text
  	vscclrm	{d0, d1, d2, d3, vpr}

Assembling returns the correct encoding with or without `mve.fp`:

  $ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
  	.text
  	vscclrm	{d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]
  $ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
  	.text
  	vscclrm	{d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]

The problem seems to be in the TableGen description of VSCCLRMD. The least significant bit should be set to zero.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68025

Files:
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/test/MC/ARM/vscclrm-asm.s
  llvm/test/MC/Disassembler/ARM/vscclrm.txt


Index: llvm/test/MC/Disassembler/ARM/vscclrm.txt
===================================================================
--- llvm/test/MC/Disassembler/ARM/vscclrm.txt
+++ llvm/test/MC/Disassembler/ARM/vscclrm.txt
@@ -1,5 +1,6 @@
 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding %s 2>&1 | FileCheck %s
-
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding %s 2>&1 \
+# RUN: | FileCheck --check-prefix=CHECK-MVE-FP %s
 
 [0x9f 0xec 0x04 0x0a]
 # CHECK: vscclrm {s0, s1, s2, s3, vpr}
@@ -16,6 +17,9 @@
 [0x9f,0xec,0x04,0x0b]
 # CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
 
+[0x9f,0xec,0x08,0x0b]
+# CHECK-MVE-FP: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]
+
 [0x9f,0xec,0x06,0x5b]
 # CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
 
Index: llvm/test/MC/ARM/vscclrm-asm.s
===================================================================
--- llvm/test/MC/ARM/vscclrm-asm.s
+++ llvm/test/MC/ARM/vscclrm-asm.s
@@ -3,6 +3,8 @@
 // RUN:   FileCheck --check-prefix=ERROR < %t %s
 // RUN: not llvm-mc -triple=thumbv8.1m.main-arm-none-eabi -mattr=-8msecext < %s 2>%t
 // RUN: FileCheck --check-prefix=NOSEC < %t %s
+// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \
+// RUN: | FileCheck --check-prefix=CHECK-MVE-FP %s
 
 // CHECK: vscclrm            {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a]
 // NOSEC: instruction requires: ARMv8-M Security Extensions
@@ -21,6 +23,9 @@
 // CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
 vscclrm {d0-d1, vpr}
 
+// CHECK-MVE-FP: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]
+vscclrm {d0-d3, vpr}
+
 // CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
 vscclrm {d5-d7, vpr}
 
Index: llvm/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2618,7 +2618,8 @@
   let Inst{21-16} = 0b011111;
   let Inst{15-12} = regs{11-8};
   let Inst{11-8} = 0b1011;
-  let Inst{7-0} = regs{7-0};
+  let Inst{7-1} = regs{7-1};
+  let Inst{0} = 0;
 
   let DecoderMethod = "DecodeVSCCLRM";
 


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