[llvm] r372812 - [AArch64][GlobalISel] Tweak legalization rule for G_BSWAP to handle widening s16.

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Tue Sep 24 21:52:42 2019
New Revision: 372812

URL: http://llvm.org/viewvc/llvm-project?rev=372812&view=rev
Log:
[AArch64][GlobalISel] Tweak legalization rule for G_BSWAP to handle widening s16.

Added:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=372812&r1=372811&r2=372812&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Tue Sep 24 21:52:42 2019
@@ -82,7 +82,7 @@ AArch64LegalizerInfo::AArch64LegalizerIn
 
   getActionDefinitionsBuilder(G_BSWAP)
       .legalFor({s32, s64, v4s32, v2s32, v2s64})
-      .clampScalar(0, s16, s64)
+      .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir?rev=372812&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir Tue Sep 24 21:52:42 2019
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64"
+
+  declare i16 @llvm.bswap.i16(i16) #0
+
+  define i16 @bswap_s16(i16 %a) { ret i16 0 }
+
+  attributes #0 = { nounwind readnone speculatable willreturn }
+
+...
+---
+name:            bswap_s16
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$w0' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1:
+    liveins: $w0
+
+    ; CHECK-LABEL: name: bswap_s16
+    ; CHECK: liveins: $w0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: $w0 = COPY [[COPY2]](s32)
+    ; CHECK: RET_ReallyLR implicit $w0
+    %1:_(s32) = COPY $w0
+    %0:_(s16) = G_TRUNC %1(s32)
+    %2:_(s16) = G_BSWAP %0
+    %3:_(s32) = G_ANYEXT %2(s16)
+    $w0 = COPY %3(s32)
+    RET_ReallyLR implicit $w0
+
+...