[PATCH] D67904: [ARM][MVE] More invalidForTailPredication insts

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Exactly which instructions can and cannot go into tail predicated loops is still a bit of a mystery to me. As we talked about, a whitelist may be simpler than a blacklist to make sure we account for everything. (Thats maybe an approach if this ends up needing more in the future).

One thing I thought of, some lane moves may go through standard vmovs, or the vmovx and vins fp16 instructions. Also will interleaved fp instructions be fine in the same loop?



================
Comment at: lib/Target/ARM/ARMInstrMVE.td:1945
 
 def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
                       (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
----------------
This has a cross beat carry, although I'm not sure that makes it invalid for tail predication.


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:1976
 
 class MVE_VMOVL<string iname, string suffix, bits<2> sz, bit U,
               list<dag> pattern=[]>
----------------
VMOVL is used to perform widening.


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:2089
 
 defm MVE_VSHLL_lws8  : MVE_VSHLL_lw<"vshll", "s8",  0b00, 0b0, "$Qd, $Qm, #8">;
 defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
----------------
VSHLL?


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:3365
 
 class MVE_VCMUL<string iname, string suffix, bit size, string cstr="", list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
----------------
Some of the complex instructions needed earlyclobber on them as they reach cross beat.


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:3387
 
 class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
                 bit T, string cstr, list<dag> pattern=[]>
----------------
VMULL?


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:3489
 
 class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
                   list<dag> pattern=[]>
----------------
Is anything that is top/bottom a problem?


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:3536
 
 class MVE_VADCSBC<string iname, bit I, bit subtract,
                   dag carryin, list<dag> pattern=[]>
----------------
Cross beat carry again.


================
Comment at: lib/Target/ARM/ARMInstrMVE.td:3931
 
 class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
               list<dag> pattern=[]>
----------------
VDUP puts the value into all lanes, but I presume that would be OK.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67904/new/

https://reviews.llvm.org/D67904