[llvm] r372557 - [ARM][LowOverheadLoops] Use tBcc when reverting
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 23 01:35:31 PDT 2019
Author: sam_parker
Date: Mon Sep 23 01:35:31 2019
New Revision: 372557
URL: http://llvm.org/viewvc/llvm-project?rev=372557&view=rev
Log:
[ARM][LowOverheadLoops] Use tBcc when reverting
Check the branch target ranges and use a tBcc instead of t2Bcc when
we can.
Differential Revision: https://reviews.llvm.org/D67796
Modified:
llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
Modified: llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp?rev=372557&r1=372556&r2=372557&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp Mon Sep 23 01:35:31 2019
@@ -354,8 +354,7 @@ bool ARMLowOverheadLoops::ProcessLoop(Ma
// WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
// beq that branches to the exit branch.
-// FIXME: Need to check that we're not trashing the CPSR when generating the
-// cmp. We could also try to generate a cbz if the value in LR is also in
+// TODO: We could also try to generate a cbz if the value in LR is also in
// another low register.
void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
@@ -366,9 +365,12 @@ void ARMLowOverheadLoops::RevertWhile(Ma
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::NoRegister);
+
+ MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
+ unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
+ ARM::tBcc : ARM::t2Bcc;
- // TODO: Try to use tBcc instead
- MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
+ MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
MIB.add(MI->getOperand(1)); // branch target
MIB.addImm(ARMCC::EQ); // condition code
MIB.addReg(ARM::CPSR);
@@ -391,8 +393,6 @@ void ARMLowOverheadLoops::RevertLoopDec(
}
// Generate a subs, or sub and cmp, and a branch instead of an LE.
-// FIXME: Need to check that we're not trashing the CPSR when generating
-// the cmp.
void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
@@ -405,9 +405,12 @@ void ARMLowOverheadLoops::RevertLoopEnd(
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::NoRegister);
- // TODO Try to use tBcc instead.
+ MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
+ unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
+ ARM::tBcc : ARM::t2Bcc;
+
// Create bne
- MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
+ MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
MIB.add(MI->getOperand(1)); // branch target
MIB.addImm(ARMCC::NE); // condition code
MIB.addReg(ARM::CPSR);
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll?rev=372557&r1=372556&r2=372557&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll Mon Sep 23 01:35:31 2019
@@ -16,7 +16,7 @@
; CHECK-END: .LBB0_2:
; CHECK-END: sub.w lr, lr, #1
; CHECK-END: cmp.w lr, #0
-; CHECK-END: bne.w .LBB0_3
+; CHECK-END: bne .LBB0_3
; CHECK-END: b .LBB0_4
; CHECK-END: .LBB0_3:
; CHECK-END: b .LBB0_2
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir?rev=372557&r1=372556&r2=372557&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir (original)
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir Mon Sep 23 01:35:31 2019
@@ -4,7 +4,7 @@
# CHECK-NOT: DLS
# CHECK: bb.1.for.body:
# CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
-# CHECK: t2Bcc %bb.3, 1, $cpsr
+# CHECK: tBcc %bb.3, 1, $cpsr
# CHECK: tB %bb.2, 14, $noreg
# CHECK: bb.2.for.cond.cleanup:
# CHECK: bb.3.for.header:
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir?rev=372557&r1=372556&r2=372557&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir (original)
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir Mon Sep 23 01:35:31 2019
@@ -3,7 +3,7 @@
# CHECK: bb.5.for.inc16:
# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14
# CHECK: t2CMPri $lr, 0, 14
-# CHECK: t2Bcc %bb.6, 1
+# CHECK: tBcc %bb.6, 1
# CHECK: tB %bb.2
# CHECK: bb.6.for.cond4.preheader:
Modified: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir?rev=372557&r1=372556&r2=372557&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir (original)
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir Mon Sep 23 01:35:31 2019
@@ -5,11 +5,11 @@
# CHECK: tBcc %bb.2, 3
# CHECK: bb.1.not.preheader:
# CHECK: t2CMPri renamable $lr, 0, 14
-# CHECK: t2Bcc %bb.4, 0
+# CHECK: tBcc %bb.4, 0
# CHECK: tB %bb.2
# CHECK: bb.3.while.body:
# CHECK: t2CMPri $lr, 0, 14
-# CHECK: t2Bcc %bb.3, 1
+# CHECK: tBcc %bb.3, 1
# CHECK: tB %bb.4
# CHECK: bb.4.while.end:
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