[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 221219.
luismarques marked an inline comment as done.
luismarques added a comment.

- Rebased on master;
- Addresses @lenary's static_assert concerns.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D67423.221219.patch
Type: text/x-patch
Size: 24867 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190922/7e084853/attachment-0001.bin>