[PATCH] D67898: [SDAG] Peek through bitcasts before commuting setcc operands
Pengfei Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 22 19:10:32 PDT 2019
pengfei updated this revision to Diff 221245.
pengfei added a comment.
Add testcase. Thanks @xbolva00
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67898/new/
https://reviews.llvm.org/D67898
Files:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/X86/i686-setcc-commute.ll
Index: llvm/test/CodeGen/X86/i686-setcc-commute.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/i686-setcc-commute.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686 -mattr=+avx512f -mattr=avx512vl | FileCheck %s
+
+define <2 x i64> @test(<2 x i64> %a) {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vpsubq %xmm0, %xmm1, %xmm1
+; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k1
+; CHECK-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
+; CHECK-NEXT: vmovdqa %xmm1, %xmm0
+; CHECK-NEXT: retl
+ %1 = sub <2 x i64> zeroinitializer, %a
+ %2 = icmp eq <2 x i64> %a, zeroinitializer
+ %3 = select <2 x i1> %2, <2 x i64> %a, <2 x i64> %1
+ ret <2 x i64> %3
+}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3069,7 +3069,8 @@
// -- but in reverse order -- then try to commute the operands of this setcc
// to match. A matching pair of setcc (cmp) and sub may be combined into 1
// instruction on some targets.
- if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
+ if (!isConstOrConstSplat(peekThroughBitcasts(N0)) &&
+ !isConstOrConstSplat(peekThroughBitcasts(N1)) &&
(DCI.isBeforeLegalizeOps() ||
isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
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