[PATCH] D66991: [PowerPC] Fix SH field overflow issue

[Yi-Hong Lyu via Phabricator via llvm-commits]

Yi-Hong.Lyu marked 4 inline comments as done.
Yi-Hong.Lyu added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/SH-field-overflow.mir:10
+  ; PowerPC Pre-Emit Peephole converts
+  ;   renamable $r4 = LI 0
+  ;   renamable $r5 = SRW renamable $r3, renamable $r4
----------------
jsji wrote:
> We know what exactly we want to test in MIR, so why don't we reduce this MIR test further ?
> eg:  a MIR with following lines should be sufficient for 32 bit, you can add another module for 64 bits, and that should be all.
> 
> ```
> $ cat sh-overflow.mir
> ---
> name:            special_right_shift32_0
> liveins:
>   - { reg: '$x3'}
>   - { reg: '$x4'}
> tracksRegLiveness: true
> body:             |
>   bb.0.entry:
>     liveins: $r3, $r4
>   
>     renamable $r4 = LI 0
>     renamable $r3 = SRW renamable $r3, renamable $r4
>     BLR8 implicit $lr8, implicit $rm, implicit $x3
> ...
> 
> ```
> 
Multiple passes after ppc-mi-peepholes relies on SSA form. Apparently, the test case is not in SSA form so we can't just use it.


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https://reviews.llvm.org/D66991