[PATCH] D67875: [X86] X86DAGToDAGISel::matchBEXTRFromAndImm(): if can't use BEXTR, fallback to BZHI (PR43381)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:3441-3443
   // TODO: Maybe load folding, greater than 32-bit masks, or a guarantee of LICM
   // hoisting the move immediate would make it worthwhile with a less optimal
   // BEXTR?
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So, should we then fallback to BZHI only if we manage to fold the load?


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Comment at: llvm/test/CodeGen/X86/bmi-x86_64.ll:28
+; BMI2-SLOW:       # %bb.0:
+; BMI2-SLOW-NEXT:    movl $16, %eax
+; BMI2-SLOW-NEXT:    bzhil %eax, %edi, %eax
----------------
craig.topper wrote:
> This doesn't look like an obvious improvement. The movq in the original code is basically free. So it was really 2 uops. The new code is 3 uops.
That is not what mca says, i guess it's not modelled in those sched models?
Is there any particularly good intel cpu schedule model that is in LLVM i should use as reference?

But yes, that is true.



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