[PATCH] D67799: [InstCombine] Fold a shifty implementation of clamp0.

Sat Sep 21 11:07:00 PDT 2019

spatel added a comment.

In D67799#1677779 <https://reviews.llvm.org/D67799#1677779>, @lebedev.ri wrote:

> Please change `clamp0` everywhere to `clamp negative to zero`, it wasn't obvious to what `clamp0` means until reading all of the patch.
>  This looks ok otherwise. Please wait for @spatel to comment.
>
> In D67799#1677606 <https://reviews.llvm.org/D67799#1677606>, @huihuiz wrote:
>
> > For X86, AArch64 and ARM target, backend produce better ASM with this transformation. Please refer to below examples:
>
>
> I'd agree. @spatel ?

Yes, all asm diffs look good to me. DAGCombiner knows how to convert a select with '0' false operand into something better ('max' or 'and not' instructions). I'm not sure if that will be true for the more general fold though, so more testing will be needed for those patterns.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67799/new/

https://reviews.llvm.org/D67799