[llvm] r372466 - [AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Sat Sep 21 02:21:13 2019
New Revision: 372466

URL: http://llvm.org/viewvc/llvm-project?rev=372466&view=rev
Log:
[AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>

Just add an extra case to the existing selection logic.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=372466&r1=372465&r2=372466&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Sat Sep 21 02:21:13 2019
@@ -1052,7 +1052,11 @@ bool AArch64InstructionSelector::selectV
   unsigned Opc = 0;
   unsigned NegOpc = 0;
   const TargetRegisterClass *RC = nullptr;
-  if (Ty == LLT::vector(4, 32)) {
+  if (Ty == LLT::vector(2, 64)) {
+    Opc = AArch64::SSHLv2i64;
+    NegOpc = AArch64::NEGv2i64;
+    RC = &AArch64::FPR128RegClass;
+  } else if (Ty == LLT::vector(4, 32)) {
     Opc = AArch64::SSHLv4i32;
     NegOpc = AArch64::NEGv4i32;
     RC = &AArch64::FPR128RegClass;

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir?rev=372466&r1=372465&r2=372466&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir Sat Sep 21 02:21:13 2019
@@ -118,3 +118,33 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            ashr_v4i64
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: fpr }
+machineFunctionInfo: {}
+body:             |
+  bb.1:
+    liveins: $q0, $q1
+
+    ; CHECK-LABEL: name: ashr_v4i64
+    ; CHECK: liveins: $q0, $q1
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK: [[NEGv2i64_:%[0-9]+]]:fpr128 = NEGv2i64 [[COPY1]]
+    ; CHECK: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]]
+    ; CHECK: $q0 = COPY [[SSHLv2i64_]]
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:fpr(<2 x s64>) = COPY $q0
+    %1:fpr(<2 x s64>) = COPY $q1
+    %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>)
+    $q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit $q0
+
+...