[llvm] r372435 - [SystemZ] Support z15 processor name

Fri Sep 20 16:04:46 PDT 2019

Author: uweigand
Date: Fri Sep 20 16:04:45 2019
New Revision: 372435

URL: http://llvm.org/viewvc/llvm-project?rev=372435&view=rev
Log:
[SystemZ] Support z15 processor name

The recently announced IBM z15 processor implements the architecture
already supported as "arch13" in LLVM.  This patch adds support for
"z15" as an alternate architecture name for arch13.

The patch also uses z15 in a number of places where we used arch13
as long as the official name was not yet announced.


Added:
    llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ15.td
      - copied, changed from r372434, llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td
    llvm/trunk/test/MC/Disassembler/SystemZ/insns-z15.txt
      - copied, changed from r372434, llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt
    llvm/trunk/test/MC/SystemZ/insn-bad-z15.s
      - copied, changed from r372434, llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s
    llvm/trunk/test/MC/SystemZ/insn-good-z15.s
      - copied, changed from r372434, llvm/trunk/test/MC/SystemZ/insn-good-arch13.s
Removed:
    llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td
    llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt
    llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s
    llvm/trunk/test/MC/SystemZ/insn-good-arch13.s
Modified:
    llvm/trunk/lib/Support/Host.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
    llvm/trunk/lib/Target/SystemZ/SystemZSchedule.td
    llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
    llvm/trunk/test/Analysis/CostModel/SystemZ/fp-cast.ll
    llvm/trunk/test/Analysis/CostModel/SystemZ/intrinsics.ll
    llvm/trunk/test/Analysis/CostModel/SystemZ/logic-miscext3.ll
    llvm/trunk/test/CodeGen/SystemZ/cond-move-01.ll
    llvm/trunk/test/CodeGen/SystemZ/cond-move-02.ll
    llvm/trunk/test/CodeGen/SystemZ/cond-move-03.ll
    llvm/trunk/test/CodeGen/SystemZ/cond-move-06.ll
    llvm/trunk/test/CodeGen/SystemZ/cond-move-07.ll
    llvm/trunk/test/CodeGen/SystemZ/cond-move-08.mir
    llvm/trunk/test/CodeGen/SystemZ/ctpop-02.ll
    llvm/trunk/test/CodeGen/SystemZ/not-01.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-01.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-02.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-03.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-04.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-05.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-06.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-bswap-07.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-conv-03.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-eswap-01.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-eswap-02.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-03.ll
    llvm/trunk/test/CodeGen/SystemZ/vec-strict-conv-03.ll

Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================

--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Fri Sep 20 16:04:45 2019
@@ -316,7 +316,7 @@ StringRef sys::detail::getHostCPUNameFor
         unsigned int Id;
         if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
           if (Id >= 8561 && HaveVectorSupport)
-            return "arch13";
+            return "z15";
           if (Id >= 3906 && HaveVectorSupport)
             return "z14";
           if (Id >= 2964 && HaveVectorSupport)

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Fri Sep 20 16:04:45 2019
@@ -258,7 +258,7 @@ SystemZTargetLowering::SystemZTargetLowe
   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
 
-  // On arch13 we have native support for a 64-bit CTPOP.
+  // On z15 we have native support for a 64-bit CTPOP.
   if (Subtarget.hasMiscellaneousExtensions3()) {
     setOperationAction(ISD::CTPOP, MVT::i32, Promote);
     setOperationAction(ISD::CTPOP, MVT::i64, Legal);

Modified: llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZProcessors.td Fri Sep 20 16:04:45 2019
@@ -35,5 +35,6 @@ def : ProcessorModel<"z13", Z13Model, Ar
 def : ProcessorModel<"arch12", Z14Model, Arch12SupportedFeatures.List>;
 def : ProcessorModel<"z14", Z14Model, Arch12SupportedFeatures.List>;
 
-def : ProcessorModel<"arch13", Arch13Model, Arch13SupportedFeatures.List>;
+def : ProcessorModel<"arch13", Z15Model, Arch13SupportedFeatures.List>;
+def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSchedule.td?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSchedule.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSchedule.td Fri Sep 20 16:04:45 2019
@@ -59,7 +59,7 @@ def VBU : SchedWrite; // Virtual branchi
 
 def MCD : SchedWrite; // Millicode
 
-include "SystemZScheduleArch13.td"
+include "SystemZScheduleZ15.td"
 include "SystemZScheduleZ14.td"
 include "SystemZScheduleZ13.td"
 include "SystemZScheduleZEC12.td"

Removed: llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td?rev=372434&view=auto
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td (removed)
@@ -1,1695 +0,0 @@
-//-- SystemZScheduleArch13.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the machine model for Arch13 to support instruction
-// scheduling and other instruction cost heuristics.
-//
-// Pseudos expanded right after isel do not need to be modelled here.
-//
-//===----------------------------------------------------------------------===//
-
-def Arch13Model : SchedMachineModel {
-
-    let UnsupportedFeatures = Arch13UnsupportedFeatures.List;
-
-    let IssueWidth = 6;             // Number of instructions decoded per cycle.
-    let MicroOpBufferSize = 60;     // Issue queues
-    let LoadLatency = 1;            // Optimistic load latency.
-
-    let PostRAScheduler = 1;
-
-    // Extra cycles for a mispredicted branch.
-    let MispredictPenalty = 20;
-}
-
-let SchedModel = Arch13Model in  {
-// These definitions need the SchedModel value. They could be put in a
-// subtarget common include file, but it seems the include system in Tablegen
-// currently (2016) rejects multiple includes of same file.
-
-// Decoder grouping rules
-let NumMicroOps = 1 in {
-  def : WriteRes<NormalGr, []>;
-  def : WriteRes<BeginGroup, []> { let BeginGroup  = 1; }
-  def : WriteRes<EndGroup, []>   { let EndGroup    = 1; }
-}
-def : WriteRes<Cracked, []> {
-  let NumMicroOps = 2;
-  let BeginGroup  = 1;
-}
-def : WriteRes<GroupAlone, []> {
-  let NumMicroOps = 3;
-  let BeginGroup  = 1;
-  let EndGroup    = 1;
-}
-def : WriteRes<GroupAlone2, []> {
-  let NumMicroOps = 6;
-  let BeginGroup  = 1;
-  let EndGroup    = 1;
-}
-def : WriteRes<GroupAlone3, []> {
-  let NumMicroOps = 9;
-  let BeginGroup  = 1;
-  let EndGroup    = 1;
-}
-
-// Incoming latency removed from the register operand which is used together
-// with a memory operand by the instruction.
-def : ReadAdvance<RegReadAdv, 4>;
-
-// LoadLatency (above) is not used for instructions in this file. This is
-// instead the role of LSULatency, which is the latency value added to the
-// result of loads and instructions with folded memory operands.
-def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
-
-let NumMicroOps = 0 in {
-  foreach L = 1-30 in
-    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
-}
-
-// Execution units.
-def Arch13_FXaUnit     : ProcResource<2>;
-def Arch13_FXbUnit     : ProcResource<2>;
-def Arch13_LSUnit      : ProcResource<2>;
-def Arch13_VecUnit     : ProcResource<2>;
-def Arch13_VecFPdUnit  : ProcResource<2> { let BufferSize = 1; /* blocking */ }
-def Arch13_VBUnit      : ProcResource<2>;
-def Arch13_MCD         : ProcResource<1>;
-
-// Subtarget specific definitions of scheduling resources.
-let NumMicroOps = 0 in {
-  def : WriteRes<FXa, [Arch13_FXaUnit]>;
-  def : WriteRes<FXb, [Arch13_FXbUnit]>;
-  def : WriteRes<LSU, [Arch13_LSUnit]>;
-  def : WriteRes<VecBF,  [Arch13_VecUnit]>;
-  def : WriteRes<VecDF,  [Arch13_VecUnit]>;
-  def : WriteRes<VecDFX, [Arch13_VecUnit]>;
-  def : WriteRes<VecMul,  [Arch13_VecUnit]>;
-  def : WriteRes<VecStr,  [Arch13_VecUnit]>;
-  def : WriteRes<VecXsPm, [Arch13_VecUnit]>;
-  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
-    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Arch13_FXaUnit]>;
-    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Arch13_FXbUnit]>;
-    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Arch13_LSUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Arch13_VecUnit]>;
-  }}
-
-  def : WriteRes<VecFPd,  [Arch13_VecFPdUnit]> { let ResourceCycles = [30]; }
-
-  def : WriteRes<VBU,     [Arch13_VBUnit]>; // Virtual Branching Unit
-}
-
-def : WriteRes<MCD, [Arch13_MCD]> { let NumMicroOps = 3;
-                                    let BeginGroup  = 1;
-                                    let EndGroup    = 1; }
-
-// -------------------------- INSTRUCTIONS ---------------------------------- //
-
-// InstRW constructs have been used in order to preserve the
-// readability of the InstrInfo files.
-
-// For each instruction, as matched by a regexp, provide a list of
-// resources that it needs. These will be combined into a SchedClass.
-
-//===----------------------------------------------------------------------===//
-// Stack allocation
-//===----------------------------------------------------------------------===//
-
-// Pseudo -> LA / LAY
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ADJDYNALLOC$")>;
-
-//===----------------------------------------------------------------------===//
-// Branch instructions
-//===----------------------------------------------------------------------===//
-
-// Branch
-def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
-def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?J(G)?(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
-def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
-def : InstRW<[WLat1, FXa, FXb, GroupAlone], (instregex "BRCTH$")>;
-def : InstRW<[WLat1, FXa, FXb, GroupAlone], (instregex "BCT(G)?(R)?$")>;
-def : InstRW<[WLat1, FXa2, FXb2, GroupAlone2],
-             (instregex "B(R)?X(H|L).*$")>;
-
-// Compare and branch
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb2, GroupAlone],
-             (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Trap instructions
-//===----------------------------------------------------------------------===//
-
-// Trap
-def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Cond)?Trap$")>;
-
-// Compare and trap
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CL(G)?RT(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CL(F|G)IT(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Call and return instructions
-//===----------------------------------------------------------------------===//
-
-// Call
-def : InstRW<[WLat1, VBU, FXa2, GroupAlone], (instregex "(Call)?BRAS$")>;
-def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BRASL$")>;
-def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
-def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
-
-// Return
-def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn$")>;
-
-//===----------------------------------------------------------------------===//
-// Move instructions
-//===----------------------------------------------------------------------===//
-
-// Moves
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
-
-// Move character
-def : InstRW<[WLat1, FXb, LSU3, GroupAlone], (instregex "MVC$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVCL(E|U)?$")>;
-def : InstRW<[WLat1, LSU2, GroupAlone], (instregex "MVCRL$")>;
-
-// Pseudo -> reg move
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "COPY(_TO_REGCLASS)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "EXTRACT_SUBREG$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "INSERT_SUBREG$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "REG_SEQUENCE$")>;
-
-// Loads
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
-def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIH(F|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>;
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
-
-// Load and zero rightmost byte
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;
-
-// Load and trap
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "L(FH|G)?AT$")>;
-
-// Load and test
-def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXa, NormalGr], (instregex "LT(G)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LT(G)?R$")>;
-
-// Stores
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST128$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
-
-// String moves.
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVST$")>;
-
-//===----------------------------------------------------------------------===//
-// Conditional move instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOCRMux$")>;
-def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|FH)?R(Asm.*)?$")>;
-def : InstRW<[WLat2, FXa, NormalGr], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>;
-def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr],
-             (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>;
-
-def : InstRW<[WLat2, FXa, NormalGr], (instregex "SELRMux$")>;
-def : InstRW<[WLat2, FXa, NormalGr], (instregex "SEL(G|FH)?R(Asm.*)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Sign extensions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "L(B|H|G)R$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(B|H|F)R$")>;
-
-def : InstRW<[WLat1LSU, WLat1LSU, FXa, LSU, NormalGr], (instregex "LTGF$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LTGFR$")>;
-
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(Y)?$")>;
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(B|H|F)$")>;
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
-
-//===----------------------------------------------------------------------===//
-// Zero extensions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLG(C|H|F|T)R$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LL(C|H)H$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
-
-// Load and zero rightmost byte
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLZRGF$")>;
-
-// Load and trap
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "LLG(F|T)?AT$")>;
-
-//===----------------------------------------------------------------------===//
-// Truncations
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STCM(H|Y)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Multi-register moves
-//===----------------------------------------------------------------------===//
-
-// Load multiple (estimated average of 5 ops)
-def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LM(H|Y|G)?$")>;
-
-// Load multiple disjoint
-def : InstRW<[WLat30, WLat30, MCD], (instregex "LMD$")>;
-
-// Store multiple
-def : InstRW<[WLat1, LSU2, FXb3, GroupAlone], (instregex "STM(G|H|Y)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Byte swaps
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LRV(G)?R$")>;
-def : InstRW<[WLat1LSU, FXa, LSU, NormalGr], (instregex "LRV(G|H)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STRV(G|H)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "MVCIN$")>;
-
-//===----------------------------------------------------------------------===//
-// Load address instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LA(Y|RL)?$")>;
-
-// Load the Global Offset Table address ( -> larl )
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "GOT$")>;
-
-//===----------------------------------------------------------------------===//
-// Absolute and Negation
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, WLat1, FXa, NormalGr], (instregex "LP(G)?R$")>;
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "L(N|P)GFR$")>;
-def : InstRW<[WLat1, WLat1, FXa, NormalGr], (instregex "LN(R|GR)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LC(R|GR)$")>;
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "LCGFR$")>;
-
-//===----------------------------------------------------------------------===//
-// Insertion
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr], (instregex "IC(Y)?$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "IC32(Y)?$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, WLat1LSU, FXa, LSU, NormalGr],
-             (instregex "ICM(H|Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "II(F|H|L)Mux$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "IIHF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "IIHH(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "IIHL(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "IILF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "IILH(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "IILL(64)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Addition
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "A(Y)?$")>;
-def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "AH(Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AIH$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AFI(Mux)?$")>;
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "AG$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AGFI$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AGHI(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AGR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AHI(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AHIMux(K)?$")>;
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "AL(Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AL(FI|HSIK)$")>;
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "ALG(F)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALGHSIK$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALGF(I|R)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALGR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "AR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "A(L)?HHHR$")>;
-def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "A(L)?HHLR$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ALSIH(N)?$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "A(L)?(G)?SI$")>;
-
-// Logical addition with carry
-def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, GroupAlone],
-             (instregex "ALC(G)?$")>;
-def : InstRW<[WLat2, WLat2, FXa, GroupAlone], (instregex "ALC(G)?R$")>;
-
-// Add with sign extension (16/32 -> 64)
-def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "AG(F|H)$")>;
-def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "AGFR$")>;
-
-//===----------------------------------------------------------------------===//
-// Subtraction
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "S(G|Y)?$")>;
-def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "SH(Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SGR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLFI$")>;
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "SL(G|GF|Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLGF(I|R)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLGR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "S(L)?HHHR$")>;
-def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "S(L)?HHLR$")>;
-
-// Subtraction with borrow
-def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, GroupAlone],
-             (instregex "SLB(G)?$")>;
-def : InstRW<[WLat2, WLat2, FXa, GroupAlone], (instregex "SLB(G)?R$")>;
-
-// Subtraction with sign extension (16/32 -> 64)
-def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "SG(F|H)$")>;
-def : InstRW<[WLat2, WLat2, FXa, NormalGr], (instregex "SGFR$")>;
-
-//===----------------------------------------------------------------------===//
-// AND
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "N(G|Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NGR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NI(FMux|HMux|LMux)$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "NI(Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NIHF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NIHH(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NIHL(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NILF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NILH(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NILL(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NR(K)?$")>;
-def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "NC$")>;
-
-//===----------------------------------------------------------------------===//
-// OR
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "O(G|Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OGR(K)?$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "OI(Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OI(FMux|HMux|LMux)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OIHF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OIHH(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OIHL(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OILF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OILH(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OILL(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OR(K)?$")>;
-def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "OC$")>;
-
-//===----------------------------------------------------------------------===//
-// XOR
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "X(G|Y)?$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "XI(Y)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "XIFMux$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "XGR(K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "XIHF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "XILF(64)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "XR(K)?$")>;
-def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "XC$")>;
-
-//===----------------------------------------------------------------------===//
-// Combined logical operations
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
-
-//===----------------------------------------------------------------------===//
-// Multiplication
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat5LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "MS(GF|Y)?$")>;
-def : InstRW<[WLat5, FXa, NormalGr], (instregex "MS(R|FI)$")>;
-def : InstRW<[WLat7LSU, RegReadAdv, FXa, LSU, NormalGr], (instregex "MSG$")>;
-def : InstRW<[WLat7, FXa, NormalGr], (instregex "MSGR$")>;
-def : InstRW<[WLat5, FXa, NormalGr], (instregex "MSGF(I|R)$")>;
-def : InstRW<[WLat8LSU, RegReadAdv, FXa2, LSU, GroupAlone], (instregex "MLG$")>;
-def : InstRW<[WLat8, FXa2, GroupAlone], (instregex "MLGR$")>;
-def : InstRW<[WLat4, FXa, NormalGr], (instregex "MGHI$")>;
-def : InstRW<[WLat4, FXa, NormalGr], (instregex "MHI$")>;
-def : InstRW<[WLat4LSU, RegReadAdv, FXa, LSU, NormalGr], (instregex "MH(Y)?$")>;
-def : InstRW<[WLat6, FXa2, GroupAlone], (instregex "M(L)?R$")>;
-def : InstRW<[WLat6LSU, RegReadAdv, FXa2, LSU, GroupAlone],
-             (instregex "M(FY|L)?$")>;
-def : InstRW<[WLat8, RegReadAdv, FXa, LSU, NormalGr], (instregex "MGH$")>;
-def : InstRW<[WLat12, RegReadAdv, FXa2, LSU, GroupAlone], (instregex "MG$")>;
-def : InstRW<[WLat8, FXa2, GroupAlone], (instregex "MGRK$")>;
-def : InstRW<[WLat6LSU, WLat6LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "MSC$")>;
-def : InstRW<[WLat8LSU, WLat8LSU, RegReadAdv, FXa, LSU, NormalGr],
-             (instregex "MSGC$")>;
-def : InstRW<[WLat6, WLat6, FXa, NormalGr], (instregex "MSRKC$")>;
-def : InstRW<[WLat8, WLat8, FXa, NormalGr], (instregex "MSGRKC$")>;
-
-//===----------------------------------------------------------------------===//
-// Division and remainder
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DR$")>;
-def : InstRW<[WLat30, RegReadAdv, FXa4, LSU, GroupAlone2], (instregex "D$")>;
-def : InstRW<[WLat30, FXa2, GroupAlone], (instregex "DSG(F)?R$")>;
-def : InstRW<[WLat30, RegReadAdv, FXa2, LSU, GroupAlone2],
-             (instregex "DSG(F)?$")>;
-def : InstRW<[WLat20, FXa4, GroupAlone], (instregex "DLR$")>;
-def : InstRW<[WLat30, FXa4, GroupAlone], (instregex "DLGR$")>;
-def : InstRW<[WLat30, RegReadAdv, FXa4, LSU, GroupAlone2],
-             (instregex "DL(G)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Shifts
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLL(G|K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SRL(G|K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SRA(G|K)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "SLA(G|K)?$")>;
-def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
-             (instregex "S(L|R)D(A|L)$")>;
-
-// Rotate
-def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
-
-// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
-
-// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
-
-//===----------------------------------------------------------------------===//
-// Comparison
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
-             (instregex "C(G|Y|Mux)?$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CRL$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(F|H)I(Mux)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CG(F|H)I$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(G)?R$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CIH$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CHF$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CHSI$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
-             (instregex "CL(Y|Mux)?$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLFHSI$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLFI(Mux)?$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CLG$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLG(HRL|HSI)$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CLGF$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLGFRL$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLGF(I|R)$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLGR$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLGRL$")>;
-def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CLHF$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLIH$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLI(Y)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "CLR$")>;
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "CLRL$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "C(L)?HHR$")>;
-def : InstRW<[WLat2, FXb, NormalGr], (instregex "C(L)?HLR$")>;
-
-// Compare halfword
-def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CH(Y)?$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "CHRL$")>;
-def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "CGHRL$")>;
-def : InstRW<[WLat2LSU, FXa, FXb, LSU, Cracked], (instregex "CHHSI$")>;
-
-// Compare with sign extension (32 -> 64)
-def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGF$")>;
-def : InstRW<[WLat2LSU, FXb, LSU, NormalGr], (instregex "CGFRL$")>;
-def : InstRW<[WLat2, FXb, NormalGr], (instregex "CGFR$")>;
-
-// Compare logical character
-def : InstRW<[WLat6, FXb, LSU2, Cracked], (instregex "CLC$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLCL(E|U)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLST$")>;
-
-// Test under mask
-def : InstRW<[WLat1LSU, FXb, LSU, NormalGr], (instregex "TM(Y)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TM(H|L)Mux$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMHH(64)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMHL(64)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMLH(64)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TMLL(64)?$")>;
-
-// Compare logical characters under mask
-def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
-             (instregex "CLM(H|Y)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Prefetch and execution hint
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "BPP$")>;
-def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "NIAI$")>;
-
-//===----------------------------------------------------------------------===//
-// Atomic operations
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, EndGroup], (instregex "Serialize$")>;
-
-def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAA(G)?$")>;
-def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAAL(G)?$")>;
-def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAN(G)?$")>;
-def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAO(G)?$")>;
-def : InstRW<[WLat2LSU, WLat2LSU, FXb, LSU, NormalGr], (instregex "LAX(G)?$")>;
-
-// Test and set
-def : InstRW<[WLat2LSU, FXb, LSU, EndGroup], (instregex "TS$")>;
-
-// Compare and swap
-def : InstRW<[WLat3LSU, WLat3LSU, FXa, FXb, LSU, GroupAlone],
-             (instregex "CS(G|Y)?$")>;
-
-// Compare double and swap
-def : InstRW<[WLat6LSU, WLat6LSU, FXa3, FXb2, LSU, GroupAlone2],
-             (instregex "CDS(Y)?$")>;
-def : InstRW<[WLat15, WLat15, FXa2, FXb4, LSU3,
-              GroupAlone3], (instregex "CDSG$")>;
-
-// Compare and swap and store
-def : InstRW<[WLat30, MCD], (instregex "CSST$")>;
-
-// Perform locked operation
-def : InstRW<[WLat30, MCD], (instregex "PLO$")>;
-
-// Load/store pair from/to quadword
-def : InstRW<[WLat4LSU, LSU2, GroupAlone], (instregex "LPQ$")>;
-def : InstRW<[WLat1, FXb2, LSU, GroupAlone], (instregex "STPQ$")>;
-
-// Load pair disjoint
-def : InstRW<[WLat1LSU, WLat1LSU, LSU2, GroupAlone], (instregex "LPD(G)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Translate and convert
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "TR$")>;
-def : InstRW<[WLat30, WLat30, WLat30, FXa3, LSU2, GroupAlone2],
-             (instregex "TRT$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRTR$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "TRE$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRT(R)?E(Opt)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TR(T|O)(T|O)(Opt)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD],
-             (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Message-security assist
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD],
-             (instregex "KM(C|F|O|CTR|A)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD],
-             (instregex "(KIMD|KLMD|KMAC|KDSA)$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD],
-             (instregex "(PCC|PPNO|PRNO)$")>;
-
-//===----------------------------------------------------------------------===//
-// Guarded storage
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LGG$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLGFSG$")>;
-def : InstRW<[WLat30, MCD], (instregex "(L|ST)GSC$")>;
-
-//===----------------------------------------------------------------------===//
-// Decimal arithmetic
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat20, RegReadAdv, FXb, VecDF2, LSU2, GroupAlone2],
-             (instregex "CVBG$")>;
-def : InstRW<[WLat20, RegReadAdv, FXb, VecDF, LSU, GroupAlone2],
-             (instregex "CVB(Y)?$")>;
-def : InstRW<[WLat1, FXb3, VecDF4, LSU, GroupAlone3], (instregex "CVDG$")>;
-def : InstRW<[WLat1, FXb2, VecDF, LSU, GroupAlone2], (instregex "CVD(Y)?$")>;
-def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "MV(N|O|Z)$")>;
-def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "(PACK|PKA|PKU)$")>;
-def : InstRW<[WLat12, LSU5, GroupAlone], (instregex "UNPK(A|U)$")>;
-def : InstRW<[WLat1, FXb, LSU2, Cracked], (instregex "UNPK$")>;
-
-def : InstRW<[WLat5LSU, FXb, VecDFX, LSU3, GroupAlone2],
-             (instregex "(A|S|ZA)P$")>;
-def : InstRW<[WLat1, FXb, VecDFX2, LSU3, GroupAlone2], (instregex "MP$")>;
-def : InstRW<[WLat1, FXb, VecDFX4, LSU3, GroupAlone2], (instregex "DP$")>;
-def : InstRW<[WLat15, FXb, VecDFX2, LSU2, GroupAlone3], (instregex "SRP$")>;
-def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
-def : InstRW<[WLat3LSU, VecDFX, LSU, Cracked], (instregex "TP$")>;
-def : InstRW<[WLat30, MCD], (instregex "ED(MK)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Access registers
-//===----------------------------------------------------------------------===//
-
-// Extract/set/copy access register
-def : InstRW<[WLat3, LSU, NormalGr], (instregex "(EAR|SAR|CPYA)$")>;
-
-// Load address extended
-def : InstRW<[WLat5, LSU, FXa, Cracked], (instregex "LAE(Y)?$")>;
-
-// Load/store access multiple (not modeled precisely)
-def : InstRW<[WLat20, WLat20, LSU5, GroupAlone], (instregex "LAM(Y)?$")>;
-def : InstRW<[WLat1, LSU5, FXb, GroupAlone2], (instregex "STAM(Y)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Program mask and addressing mode
-//===----------------------------------------------------------------------===//
-
-// Insert Program Mask
-def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
-
-// Set Program Mask
-def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
-
-// Branch and link
-def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "BAL(R)?$")>;
-
-// Test addressing mode
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TAM$")>;
-
-// Set addressing mode
-def : InstRW<[WLat1, FXb, EndGroup], (instregex "SAM(24|31|64)$")>;
-
-// Branch (and save) and set mode.
-def : InstRW<[WLat1, FXa, FXb, GroupAlone], (instregex "BSM$")>;
-def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "BASSM$")>;
-
-//===----------------------------------------------------------------------===//
-// Transactional execution
-//===----------------------------------------------------------------------===//
-
-// Transaction begin
-def : InstRW<[WLat9, LSU2, FXb5, GroupAlone2], (instregex "TBEGIN(C)?$")>;
-
-// Transaction end
-def : InstRW<[WLat1, FXb, GroupAlone], (instregex "TEND$")>;
-
-// Transaction abort
-def : InstRW<[WLat30, MCD], (instregex "TABORT$")>;
-
-// Extract Transaction Nesting Depth
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "ETND$")>;
-
-// Nontransactional store
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "NTSTG$")>;
-
-//===----------------------------------------------------------------------===//
-// Processor assist
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, GroupAlone], (instregex "PPA$")>;
-
-//===----------------------------------------------------------------------===//
-// Miscellaneous Instructions.
-//===----------------------------------------------------------------------===//
-
-// Find leftmost one
-def : InstRW<[WLat5, WLat5, FXa2, GroupAlone], (instregex "FLOGR$")>;
-
-// Population count
-def : InstRW<[WLat3, WLat3, FXa, NormalGr], (instregex "POPCNT(Opt)?$")>;
-
-// String instructions
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "SRST(U)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CUSE$")>;
-
-// Various complex instructions
-def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CFC$")>;
-def : InstRW<[WLat30, WLat30, WLat30, WLat30, WLat30, WLat30, MCD],
-             (instregex "UPT$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CKSM$")>;
-def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CMPSC$")>;
-def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "SORTL$")>;
-def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "DFLTCC$")>;
-
-// Execute
-def : InstRW<[WLat1, FXb, GroupAlone], (instregex "EX(RL)?$")>;
-
-//===----------------------------------------------------------------------===//
-// .insn directive instructions
-//===----------------------------------------------------------------------===//
-
-// An "empty" sched-class will be assigned instead of the "invalid sched-class".
-// getNumDecoderSlots() will then return 1 instead of 0.
-def : InstRW<[], (instregex "Insn.*")>;
-
-
-// ----------------------------- Floating point ----------------------------- //
-
-//===----------------------------------------------------------------------===//
-// FP: Move instructions
-//===----------------------------------------------------------------------===//
-
-// Load zero
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "LZ(DR|ER)$")>;
-def : InstRW<[WLat2, FXb2, Cracked], (instregex "LZXR$")>;
-
-// Load
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "LER$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "LD(R|R32|GR)$")>;
-def : InstRW<[WLat3, FXb, NormalGr], (instregex "LGDR$")>;
-def : InstRW<[WLat2, FXb2, GroupAlone], (instregex "LXR$")>;
-
-// Load and Test
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BR$")>;
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BRCompare$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone],
-             (instregex "LTXBR(Compare)?$")>;
-
-// Copy sign
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Load instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "LE(Y)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LD(Y|E32)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Store instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STX$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Conversion instructions
-//===----------------------------------------------------------------------===//
-
-// Load rounded
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "LEDBR(A)?$")>;
-def : InstRW<[WLat9, VecDF2, NormalGr], (instregex "L(E|D)XBR(A)?$")>;
-
-// Load lengthened
-def : InstRW<[WLat6LSU, VecBF, LSU, NormalGr], (instregex "LDEB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "LDEBR$")>;
-def : InstRW<[WLat7LSU, VecBF4, LSU, GroupAlone], (instregex "LX(E|D)B$")>;
-def : InstRW<[WLat7, VecBF4, GroupAlone], (instregex "LX(E|D)BR$")>;
-
-// Convert from fixed / logical
-def : InstRW<[WLat7, FXb, VecBF, Cracked], (instregex "C(E|D)(F|G)BR(A)?$")>;
-def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "CX(F|G)BR(A)?$")>;
-def : InstRW<[WLat7, FXb, VecBF, Cracked], (instregex "C(E|D)L(F|G)BR$")>;
-def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "CXL(F|G)BR$")>;
-
-// Convert to fixed / logical
-def : InstRW<[WLat9, WLat9, FXb, VecBF, Cracked],
-             (instregex "C(F|G)(E|D)BR(A)?$")>;
-def : InstRW<[WLat12, WLat12, FXb, VecDF2, Cracked],
-             (instregex "C(F|G)XBR(A)?$")>;
-def : InstRW<[WLat9, WLat9, FXb, VecBF, GroupAlone], (instregex "CLFEBR$")>;
-def : InstRW<[WLat9, WLat9, FXb, VecBF, Cracked], (instregex "CLFDBR$")>;
-def : InstRW<[WLat9, WLat9, FXb, VecBF, Cracked], (instregex "CLG(E|D)BR$")>;
-def : InstRW<[WLat12, WLat12, FXb, VecDF2, Cracked], (instregex "CL(F|G)XBR$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Unary arithmetic
-//===----------------------------------------------------------------------===//
-
-// Load Complement / Negative / Positive
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "L(C|N|P)(E|D)BR$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "L(C|N|P)DFR(_32)?$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "L(C|N|P)XBR$")>;
-
-// Square root
-def : InstRW<[WLat30, VecFPd, LSU, NormalGr], (instregex "SQ(E|D)B$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "SQ(E|D)BR$")>;
-def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "SQXBR$")>;
-
-// Load FP integer
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "FI(E|D)BR(A)?$")>;
-def : InstRW<[WLat10, VecDF4, GroupAlone], (instregex "FIXBR(A)?$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Binary arithmetic
-//===----------------------------------------------------------------------===//
-
-// Addition
-def : InstRW<[WLat6LSU, WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "A(E|D)B$")>;
-def : InstRW<[WLat6, WLat6, VecBF, NormalGr], (instregex "A(E|D)BR$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "AXBR$")>;
-
-// Subtraction
-def : InstRW<[WLat6LSU, WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "S(E|D)B$")>;
-def : InstRW<[WLat6, WLat6, VecBF, NormalGr], (instregex "S(E|D)BR$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "SXBR$")>;
-
-// Multiply
-def : InstRW<[WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "M(D|DE|EE)B$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "M(D|DE|EE)BR$")>;
-def : InstRW<[WLat7LSU, RegReadAdv, VecBF4, LSU, GroupAlone],
-             (instregex "MXDB$")>;
-def : InstRW<[WLat7, VecBF4, GroupAlone], (instregex "MXDBR$")>;
-def : InstRW<[WLat15, VecDF4, GroupAlone], (instregex "MXBR$")>;
-
-// Multiply and add / subtract
-def : InstRW<[WLat6LSU, RegReadAdv, RegReadAdv, VecBF2, LSU, GroupAlone],
-             (instregex "M(A|S)EB$")>;
-def : InstRW<[WLat6, VecBF, GroupAlone], (instregex "M(A|S)EBR$")>;
-def : InstRW<[WLat6LSU, RegReadAdv, RegReadAdv, VecBF2, LSU, GroupAlone],
-             (instregex "M(A|S)DB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "M(A|S)DBR$")>;
-
-// Division
-def : InstRW<[WLat30, RegReadAdv, VecFPd, LSU, NormalGr],
-             (instregex "D(E|D)B$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "D(E|D)BR$")>;
-def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "DXBR$")>;
-
-// Divide to integer
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "DI(E|D)BR$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Comparisons
-//===----------------------------------------------------------------------===//
-
-// Compare
-def : InstRW<[WLat3LSU, RegReadAdv, VecXsPm, LSU, NormalGr],
-             (instregex "(K|C)(E|D)B$")>;
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "(K|C)(E|D)BR$")>;
-def : InstRW<[WLat9, VecDF2, GroupAlone], (instregex "(K|C)XBR$")>;
-
-// Test Data Class
-def : InstRW<[WLat5, LSU, VecXsPm, NormalGr], (instregex "TC(E|D)B$")>;
-def : InstRW<[WLat10, LSU, VecDF4, GroupAlone], (instregex "TCXB$")>;
-
-//===----------------------------------------------------------------------===//
-// FP: Floating-point control register instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat4, FXa, LSU, GroupAlone], (instregex "EFPC$")>;
-def : InstRW<[WLat1, FXb, LSU, GroupAlone], (instregex "STFPC$")>;
-def : InstRW<[WLat3, LSU, GroupAlone], (instregex "SFPC$")>;
-def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LFPC$")>;
-def : InstRW<[WLat30, MCD], (instregex "SFASR$")>;
-def : InstRW<[WLat30, MCD], (instregex "LFAS$")>;
-def : InstRW<[WLat3, FXb, GroupAlone], (instregex "SRNM(B|T)?$")>;
-
-
-// --------------------- Hexadecimal floating point ------------------------- //
-
-//===----------------------------------------------------------------------===//
-// HFP: Move instructions
-//===----------------------------------------------------------------------===//
-
-// Load and Test
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)R$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXR$")>;
-
-//===----------------------------------------------------------------------===//
-// HFP: Conversion instructions
-//===----------------------------------------------------------------------===//
-
-// Load rounded
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "(LEDR|LRER)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "LEXR$")>;
-def : InstRW<[WLat9, VecDF2, NormalGr], (instregex "(LDXR|LRDR)$")>;
-
-// Load lengthened
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LDE$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "LDER$")>;
-def : InstRW<[WLat7LSU, VecBF4, LSU, GroupAlone], (instregex "LX(E|D)$")>;
-def : InstRW<[WLat7, VecBF4, GroupAlone], (instregex "LX(E|D)R$")>;
-
-// Convert from fixed
-def : InstRW<[WLat7, FXb, VecBF, Cracked], (instregex "C(E|D)(F|G)R$")>;
-def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "CX(F|G)R$")>;
-
-// Convert to fixed
-def : InstRW<[WLat9, WLat9, FXb, VecBF, Cracked], (instregex "C(F|G)(E|D)R$")>;
-def : InstRW<[WLat12, WLat12, FXb, VecDF2, Cracked], (instregex "C(F|G)XR$")>;
-
-// Convert BFP to HFP / HFP to BFP.
-def : InstRW<[WLat6, WLat6, VecBF, NormalGr], (instregex "THD(E)?R$")>;
-def : InstRW<[WLat6, WLat6, VecBF, NormalGr], (instregex "TB(E)?DR$")>;
-
-//===----------------------------------------------------------------------===//
-// HFP: Unary arithmetic
-//===----------------------------------------------------------------------===//
-
-// Load Complement / Negative / Positive
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "L(C|N|P)(E|D)R$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "L(C|N|P)XR$")>;
-
-// Halve
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "H(E|D)R$")>;
-
-// Square root
-def : InstRW<[WLat30, VecFPd, LSU, NormalGr], (instregex "SQ(E|D)$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "SQ(E|D)R$")>;
-def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "SQXR$")>;
-
-// Load FP integer
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "FI(E|D)R$")>;
-def : InstRW<[WLat10, VecDF4, GroupAlone], (instregex "FIXR$")>;
-
-//===----------------------------------------------------------------------===//
-// HFP: Binary arithmetic
-//===----------------------------------------------------------------------===//
-
-// Addition
-def : InstRW<[WLat6LSU, WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "A(E|D|U|W)$")>;
-def : InstRW<[WLat6, WLat6, VecBF, NormalGr], (instregex "A(E|D|U|W)R$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "AXR$")>;
-
-// Subtraction
-def : InstRW<[WLat6LSU, WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "S(E|D|U|W)$")>;
-def : InstRW<[WLat6, WLat6, VecBF, NormalGr], (instregex "S(E|D|U|W)R$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "SXR$")>;
-
-// Multiply
-def : InstRW<[WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "M(D|DE|E|EE)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "M(D|DE|E|EE)R$")>;
-def : InstRW<[WLat7LSU, RegReadAdv, VecBF4, LSU, GroupAlone],
-             (instregex "MXD$")>;
-def : InstRW<[WLat7, VecBF4, GroupAlone], (instregex "MXDR$")>;
-def : InstRW<[WLat30, VecDF4, GroupAlone], (instregex "MXR$")>;
-def : InstRW<[WLat7LSU, RegReadAdv, VecBF4, LSU, GroupAlone], (instregex "MY$")>;
-def : InstRW<[WLat6LSU, RegReadAdv, VecBF2, LSU, GroupAlone],
-             (instregex "MY(H|L)$")>;
-def : InstRW<[WLat7, VecBF4, GroupAlone], (instregex "MYR$")>;
-def : InstRW<[WLat6, VecBF, GroupAlone], (instregex "MY(H|L)R$")>;
-
-// Multiply and add / subtract
-def : InstRW<[WLat6LSU, RegReadAdv, RegReadAdv, VecBF2, LSU, GroupAlone],
-             (instregex "M(A|S)(E|D)$")>;
-def : InstRW<[WLat6, VecBF, GroupAlone], (instregex "M(A|S)(E|D)R$")>;
-def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, VecBF4, LSU, GroupAlone],
-             (instregex "MAY$")>;
-def : InstRW<[WLat6LSU, RegReadAdv, RegReadAdv, VecBF2, LSU, GroupAlone],
-             (instregex "MAY(H|L)$")>;
-def : InstRW<[WLat7, VecBF4, GroupAlone], (instregex "MAYR$")>;
-def : InstRW<[WLat6, VecBF, GroupAlone], (instregex "MAY(H|L)R$")>;
-
-// Division
-def : InstRW<[WLat30, RegReadAdv, VecFPd, LSU, NormalGr], (instregex "D(E|D)$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "D(E|D)R$")>;
-def : InstRW<[WLat30, VecFPd, GroupAlone], (instregex "DXR$")>;
-
-//===----------------------------------------------------------------------===//
-// HFP: Comparisons
-//===----------------------------------------------------------------------===//
-
-// Compare
-def : InstRW<[WLat6LSU, RegReadAdv, VecBF, LSU, NormalGr],
-             (instregex "C(E|D)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "C(E|D)R$")>;
-def : InstRW<[WLat10, VecDF2, GroupAlone], (instregex "CXR$")>;
-
-
-// ------------------------ Decimal floating point -------------------------- //
-
-//===----------------------------------------------------------------------===//
-// DFP: Move instructions
-//===----------------------------------------------------------------------===//
-
-// Load and Test
-def : InstRW<[WLat8, WLat8, VecDF, NormalGr], (instregex "LTDTR$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXTR$")>;
-
-//===----------------------------------------------------------------------===//
-// DFP: Conversion instructions
-//===----------------------------------------------------------------------===//
-
-// Load rounded
-def : InstRW<[WLat15, VecDF, NormalGr], (instregex "LEDTR$")>;
-def : InstRW<[WLat15, VecDF2, NormalGr], (instregex "LDXTR$")>;
-
-// Load lengthened
-def : InstRW<[WLat8, VecDF, NormalGr], (instregex "LDETR$")>;
-def : InstRW<[WLat10, VecDF4, GroupAlone], (instregex "LXDTR$")>;
-
-// Convert from fixed / logical
-def : InstRW<[WLat15, FXb, VecDF, Cracked], (instregex "CDFTR(A)?$")>;
-def : InstRW<[WLat30, FXb, VecDF, Cracked], (instregex "CDGTR(A)?$")>;
-def : InstRW<[WLat15, FXb, VecDF4, GroupAlone2], (instregex "CXFTR(A)?$")>;
-def : InstRW<[WLat30, FXb, VecDF4, GroupAlone2], (instregex "CXGTR(A)?$")>;
-def : InstRW<[WLat15, FXb, VecDF, Cracked], (instregex "CDLFTR$")>;
-def : InstRW<[WLat30, FXb, VecDF, Cracked], (instregex "CDLGTR$")>;
-def : InstRW<[WLat15, FXb, VecDF4, GroupAlone2], (instregex "CXLFTR$")>;
-def : InstRW<[WLat30, FXb, VecDF4, GroupAlone2], (instregex "CXLGTR$")>;
-
-// Convert to fixed / logical
-def : InstRW<[WLat30, WLat30, FXb, VecDF, Cracked],
-             (instregex "C(F|G)DTR(A)?$")>;
-def : InstRW<[WLat30, WLat30, FXb, VecDF2, Cracked],
-             (instregex "C(F|G)XTR(A)?$")>;
-def : InstRW<[WLat30, WLat30, FXb, VecDF, Cracked], (instregex "CL(F|G)DTR$")>;
-def : InstRW<[WLat30, WLat30, FXb, VecDF2, Cracked], (instregex "CL(F|G)XTR$")>;
-
-// Convert from / to signed / unsigned packed
-def : InstRW<[WLat9, FXb, VecDF, Cracked], (instregex "CD(S|U)TR$")>;
-def : InstRW<[WLat12, FXb2, VecDF4, GroupAlone2], (instregex "CX(S|U)TR$")>;
-def : InstRW<[WLat11, FXb, VecDF, Cracked], (instregex "C(S|U)DTR$")>;
-def : InstRW<[WLat15, FXb2, VecDF4, GroupAlone2], (instregex "C(S|U)XTR$")>;
-
-// Convert from / to zoned
-def : InstRW<[WLat8LSU, LSU, VecDF, Cracked], (instregex "CDZT$")>;
-def : InstRW<[WLat16LSU, LSU2, VecDF4, GroupAlone3], (instregex "CXZT$")>;
-def : InstRW<[WLat1, FXb, LSU, VecDF, Cracked], (instregex "CZDT$")>;
-def : InstRW<[WLat1, FXb, LSU, VecDF2, GroupAlone], (instregex "CZXT$")>;
-
-// Convert from / to packed
-def : InstRW<[WLat8LSU, LSU, VecDF, Cracked], (instregex "CDPT$")>;
-def : InstRW<[WLat16LSU, LSU2, VecDF4, GroupAlone3], (instregex "CXPT$")>;
-def : InstRW<[WLat1, FXb, LSU, VecDF, Cracked], (instregex "CPDT$")>;
-def : InstRW<[WLat1, FXb, LSU, VecDF2, GroupAlone], (instregex "CPXT$")>;
-
-// Perform floating-point operation
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "PFPO$")>;
-
-//===----------------------------------------------------------------------===//
-// DFP: Unary arithmetic
-//===----------------------------------------------------------------------===//
-
-// Load FP integer
-def : InstRW<[WLat8, VecDF, NormalGr], (instregex "FIDTR$")>;
-def : InstRW<[WLat10, VecDF4, GroupAlone], (instregex "FIXTR$")>;
-
-// Extract biased exponent
-def : InstRW<[WLat11, FXb, VecDF, Cracked], (instregex "EEDTR$")>;
-def : InstRW<[WLat11, FXb, VecDF, Cracked], (instregex "EEXTR$")>;
-
-// Extract significance
-def : InstRW<[WLat11, FXb, VecDF, Cracked], (instregex "ESDTR$")>;
-def : InstRW<[WLat12, FXb, VecDF2, Cracked], (instregex "ESXTR$")>;
-
-//===----------------------------------------------------------------------===//
-// DFP: Binary arithmetic
-//===----------------------------------------------------------------------===//
-
-// Addition
-def : InstRW<[WLat8, WLat8, VecDF, NormalGr], (instregex "ADTR(A)?$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "AXTR(A)?$")>;
-
-// Subtraction
-def : InstRW<[WLat8, WLat8, VecDF, NormalGr], (instregex "SDTR(A)?$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "SXTR(A)?$")>;
-
-// Multiply
-def : InstRW<[WLat30, VecDF, NormalGr], (instregex "MDTR(A)?$")>;
-def : InstRW<[WLat30, VecDF4, GroupAlone], (instregex "MXTR(A)?$")>;
-
-// Division
-def : InstRW<[WLat30, VecDF, NormalGr], (instregex "DDTR(A)?$")>;
-def : InstRW<[WLat30, VecDF4, GroupAlone], (instregex "DXTR(A)?$")>;
-
-// Quantize
-def : InstRW<[WLat8, WLat8, VecDF, NormalGr], (instregex "QADTR$")>;
-def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "QAXTR$")>;
-
-// Reround
-def : InstRW<[WLat9, WLat9, FXb, VecDF, Cracked], (instregex "RRDTR$")>;
-def : InstRW<[WLat11, WLat11, FXb, VecDF4, GroupAlone2], (instregex "RRXTR$")>;
-
-// Shift significand left/right
-def : InstRW<[WLat11LSU, LSU, VecDF, GroupAlone], (instregex "S(L|R)DT$")>;
-def : InstRW<[WLat11LSU, LSU, VecDF4, GroupAlone], (instregex "S(L|R)XT$")>;
-
-// Insert biased exponent
-def : InstRW<[WLat9, FXb, VecDF, Cracked], (instregex "IEDTR$")>;
-def : InstRW<[WLat11, FXb, VecDF4, GroupAlone2], (instregex "IEXTR$")>;
-
-//===----------------------------------------------------------------------===//
-// DFP: Comparisons
-//===----------------------------------------------------------------------===//
-
-// Compare
-def : InstRW<[WLat8, VecDF, NormalGr], (instregex "(K|C)DTR$")>;
-def : InstRW<[WLat9, VecDF2, GroupAlone], (instregex "(K|C)XTR$")>;
-
-// Compare biased exponent
-def : InstRW<[WLat8, VecDF, NormalGr], (instregex "CEDTR$")>;
-def : InstRW<[WLat8, VecDF, NormalGr], (instregex "CEXTR$")>;
-
-// Test Data Class/Group
-def : InstRW<[WLat15, LSU, VecDF, NormalGr], (instregex "TD(C|G)(E|D)T$")>;
-def : InstRW<[WLat15, LSU, VecDF2, GroupAlone], (instregex "TD(C|G)XT$")>;
-
-
-// --------------------------------- Vector --------------------------------- //
-
-//===----------------------------------------------------------------------===//
-// Vector: Move instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLR(32|64)?$")>;
-def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLGV(B|F|G|H)?$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "VLVG(B|F|G|H)?$")>;
-def : InstRW<[WLat3, FXb, NormalGr], (instregex "VLVGP(32)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Immediate instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VZERO$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VONE$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VGBM$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VGM(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VREPI(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VLEI(B|F|G|H)$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Loads
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(Align)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(L|BB)$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(32|64)$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLLEZ(B|F|G|H|LF)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLREP(B|F|G|H)?$")>;
-def : InstRW<[WLat2LSU, RegReadAdv, VecXsPm, LSU, NormalGr],
-             (instregex "VLE(B|F|G|H)$")>;
-def : InstRW<[WLat5LSU, RegReadAdv, FXb, LSU, VecXsPm, Cracked],
-             (instregex "VGE(F|G)$")>;
-def : InstRW<[WLat4LSU, WLat4LSU, LSU5, GroupAlone],
-             (instregex "VLM(Align)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLRL(R)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Stores
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VST(Align|L|32|64)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTE(F|G)$")>;
-def : InstRW<[WLat1, FXb, LSU, VecXsPm, Cracked], (instregex "VSTE(B|H)$")>;
-def : InstRW<[WLat1, LSU2, FXb3, GroupAlone2], (instregex "VSTM(Align)?$")>;
-def : InstRW<[WLat1, FXb2, LSU, Cracked], (instregex "VSCE(F|G)$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTRL(R)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Byte swaps
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLBR(H|F|G|Q)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLER(H|F|G)?$")>;
-def : InstRW<[WLat2LSU, RegReadAdv, VecXsPm, LSU, NormalGr],
-             (instregex "VLEBR(H|F|G)$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLLEBRZ(H|F|G|E)?$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLBRREP(H|F|G)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTBR(H|F|G|Q)?$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTER(H|F|G)?$")>;
-def : InstRW<[WLat1, FXb, LSU, VecXsPm, Cracked], (instregex "VSTEBRH$")>;
-def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTEBR(F|G)$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Selects and permutes
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMRH(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMRL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VPERM$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VPDI$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VBPERM$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VREP(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSEL$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Widening and narrowing
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VPK(F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VPKS(F|G|H)?$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VPKS(F|G|H)S$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VPKLS(F|G|H)?$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VPKLS(F|G|H)S$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSEG(B|F|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VUPH(B|F|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VUPL(B|F)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VUPLH(B|F|H|W)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VUPLL(B|F|H)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Integer arithmetic
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VA(B|F|G|H|Q|C|CQ)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VACC(B|F|G|H|Q|C|CQ)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VAVG(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VAVGL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VN(C|O|N|X)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VO(C)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VCKSM$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VCLZ(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VCTZ(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VGFM?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VGFMA(B|F|G|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VGFM(B|F|G|H)$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VLC(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VLP(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMX(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMXL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMN(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VMNL(B|F|G|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMAL(B|F)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMALE(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMALH(B|F|H|W)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMALO(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMAO(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMAE(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMAH(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VME(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMH(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VML(B|F)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMLE(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMLH(B|F|H|W)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMLO(B|F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VMO(B|F|H)?$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VMSL(G)?$")>;
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VPOPCT(B|F|G|H)?$")>;
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VERLL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VERLLV(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VERIM(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VESL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VESLV(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VESRA(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VESRAV(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VESRL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VESRLV(B|F|G|H)?$")>;
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSL(DB)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSLB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSR(A|L)$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSR(A|L)B$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSLD$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSRD$")>;
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSB(I|IQ|CBI|CBIQ)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VSCBI(B|F|G|H|Q)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VS(F|G|H|Q)?$")>;
-
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VSUM(B|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VSUMG(F|H)?$")>;
-def : InstRW<[WLat4, VecMul, NormalGr], (instregex "VSUMQ(F|G)?$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Integer comparison
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "VEC(B|F|G|H)?$")>;
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "VECL(B|F|G|H)?$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VCEQ(B|F|G|H)?$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VCEQ(B|F|G|H)S$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VCH(B|F|G|H)?$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VCH(B|F|G|H)S$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VCHL(B|F|G|H)?$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VCHL(B|F|G|H)S$")>;
-def : InstRW<[WLat4, VecStr, NormalGr], (instregex "VTM$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Floating-point arithmetic
-//===----------------------------------------------------------------------===//
-
-// Conversion and rounding
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VCFP(S|L)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VCD(L)?G$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VCD(L)?GB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WCD(L)?GB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VCE(L)?FB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WCE(L)?FB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VC(S|L)FP$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VC(L)?GD$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VC(L)?GDB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WC(L)?GDB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VC(L)?FEB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WC(L)?FEB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VL(DE|ED)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VL(DE|ED)B$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WL(DE|ED)B$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VFL(L|R)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VFL(LS|RD)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WFL(LS|RD)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WFLLD$")>;
-def : InstRW<[WLat10, VecDF2, NormalGr], (instregex "WFLRX$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VFI(DB)?$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WFIDB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VFISB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WFISB$")>;
-def : InstRW<[WLat10, VecDF2, NormalGr], (instregex "WFIXB$")>;
-
-// Sign operations
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VFPSO$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "(V|W)FPSODB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "(V|W)FPSOSB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WFPSOXB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "(V|W)FL(C|N|P)DB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "(V|W)FL(C|N|P)SB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WFL(C|N|P)XB$")>;
-
-// Minimum / maximum
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VF(MAX|MIN)$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VF(MAX|MIN)DB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WF(MAX|MIN)DB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VF(MAX|MIN)SB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WF(MAX|MIN)SB$")>;
-def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "WF(MAX|MIN)XB$")>;
-
-// Test data class
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VFTCI$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "(V|W)FTCIDB$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "(V|W)FTCISB$")>;
-def : InstRW<[WLat3, WLat3, VecDFX, NormalGr], (instregex "WFTCIXB$")>;
-
-// Add / subtract
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)DB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)DB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(A|S)SB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(A|S)SB$")>;
-def : InstRW<[WLat10, VecDF2, NormalGr], (instregex "WF(A|S)XB$")>;
-
-// Multiply / multiply-and-add/subtract
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VFM(DB)?$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WFM(D|S)B$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VFMSB$")>;
-def : InstRW<[WLat20, VecDF2, NormalGr], (instregex "WFMXB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(N)?M(A|S)$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(N)?M(A|S)DB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(N)?M(A|S)DB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "VF(N)?M(A|S)SB$")>;
-def : InstRW<[WLat6, VecBF, NormalGr], (instregex "WF(N)?M(A|S)SB$")>;
-def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "WF(N)?M(A|S)XB$")>;
-
-// Divide / square root
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "VFD$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "(V|W)FDDB$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "(V|W)FDSB$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "WFDXB$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "VFSQ$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "(V|W)FSQDB$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "(V|W)FSQSB$")>;
-def : InstRW<[WLat30, VecFPd, NormalGr], (instregex "WFSQXB$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Floating-point comparison
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VF(C|K)(E|H|HE)$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VF(C|K)(E|H|HE)DB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WFC(E|H|HE)DB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WFK(E|H|HE)DB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VF(C|K)(E|H|HE)SB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WFC(E|H|HE)SB$")>;
-def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "WFK(E|H|HE)SB$")>;
-def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "WFC(E|H|HE)XB$")>;
-def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "WFK(E|H|HE)XB$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VFC(E|H|HE)DBS$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "VFK(E|H|HE)DBS$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr],
-             (instregex "WF(C|K)(E|H|HE)DBS$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr],
-             (instregex "VF(C|K)(E|H|HE)SBS$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "WFC(E|H|HE)SBS$")>;
-def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "WFK(E|H|HE)SBS$")>;
-def : InstRW<[WLat3, WLat3, VecDFX, NormalGr], (instregex "WFC(E|H|HE)XBS$")>;
-def : InstRW<[WLat3, WLat3, VecDFX, NormalGr], (instregex "WFK(E|H|HE)XBS$")>;
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "WF(C|K)$")>;
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "WF(C|K)DB$")>;
-def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "WF(C|K)SB$")>;
-def : InstRW<[WLat3, VecDFX, NormalGr], (instregex "WF(C|K)XB$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Floating-point insertion and extraction
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "LEFR$")>;
-def : InstRW<[WLat3, FXb, NormalGr], (instregex "LFER$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: String instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VFAE(B)?$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VFAE(F|H)$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VFAE(B|F|H)S$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VFAEZ(B|F|H)$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VFAEZ(B|F|H)S$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VFEE(B|F|H|ZB|ZF|ZH)?$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr],
-             (instregex "VFEE(B|F|H|ZB|ZF|ZH)S$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VFENE(B|F|H|ZB|ZF|ZH)?$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr],
-             (instregex "VFENE(B|F|H|ZB|ZF|ZH)S$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VISTR(B|F|H)?$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VISTR(B|F|H)S$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VSTRC(B|F|H)?$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VSTRC(B|F|H)S$")>;
-def : InstRW<[WLat3, VecStr, NormalGr], (instregex "VSTRCZ(B|F|H)$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VSTRCZ(B|F|H)S$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VSTRS(B|F|H)?$")>;
-def : InstRW<[WLat4, WLat4, VecStr, NormalGr], (instregex "VSTRSZ(B|F|H)$")>;
-
-//===----------------------------------------------------------------------===//
-// Vector: Packed-decimal instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "VLIP$")>;
-def : InstRW<[WLat6, VecDFX, LSU, GroupAlone2], (instregex "VPKZ$")>;
-def : InstRW<[WLat1, VecDFX, FXb, LSU2, GroupAlone2], (instregex "VUPKZ$")>;
-def : InstRW<[WLat20, WLat20, VecDF2, FXb, GroupAlone],
-             (instregex "VCVB(G)?(Opt)?$")>;
-def : InstRW<[WLat15, WLat15, VecDF2, FXb, GroupAlone],
-             (instregex "VCVD(G)?$")>;
-def : InstRW<[WLat4, WLat4, VecDFX, NormalGr], (instregex "V(A|S)P$")>;
-def : InstRW<[WLat30, WLat30, VecDF2, GroupAlone], (instregex "VM(S)?P$")>;
-def : InstRW<[WLat30, WLat30, VecDF2, GroupAlone], (instregex "V(D|R)P$")>;
-def : InstRW<[WLat30, WLat30, VecDF2, GroupAlone], (instregex "VSDP$")>;
-def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRP$")>;
-def : InstRW<[WLat4, WLat4, VecDFX, NormalGr], (instregex "VPSOP$")>;
-def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "V(T|C)P$")>;
-
-
-// -------------------------------- System ---------------------------------- //
-
-//===----------------------------------------------------------------------===//
-// System: Program-Status Word Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, WLat30, MCD], (instregex "EPSW$")>;
-def : InstRW<[WLat20, GroupAlone3], (instregex "LPSW(E)?$")>;
-def : InstRW<[WLat3, FXa, GroupAlone], (instregex "IPK$")>;
-def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
-def : InstRW<[WLat1, LSU, EndGroup], (instregex "SSM$")>;
-def : InstRW<[WLat1, FXb, LSU, GroupAlone], (instregex "ST(N|O)SM$")>;
-def : InstRW<[WLat3, FXa, NormalGr], (instregex "IAC$")>;
-def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAC(F)?$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Control Register Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat4LSU, WLat4LSU, LSU2, GroupAlone], (instregex "LCTL(G)?$")>;
-def : InstRW<[WLat1, LSU5, FXb, GroupAlone2], (instregex "STCT(L|G)$")>;
-def : InstRW<[LSULatency, LSU, NormalGr], (instregex "E(P|S)A(I)?R$")>;
-def : InstRW<[WLat30, MCD], (instregex "SSA(I)?R$")>;
-def : InstRW<[WLat30, MCD], (instregex "ESEA$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Prefix-Register Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Storage-Key and Real Memory Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "ISKE$")>;
-def : InstRW<[WLat30, MCD], (instregex "IVSK$")>;
-def : InstRW<[WLat30, MCD], (instregex "SSKE(Opt)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "RRB(E|M)$")>;
-def : InstRW<[WLat30, MCD], (instregex "IRBM$")>;
-def : InstRW<[WLat30, MCD], (instregex "PFMF$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "TB$")>;
-def : InstRW<[WLat30, MCD], (instregex "PGIN$")>;
-def : InstRW<[WLat30, MCD], (instregex "PGOUT$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Dynamic-Address-Translation Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "IPTE(Opt)?(Opt)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "IDTE(Opt)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "CRDTE(Opt)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "PTLB$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "CSP(G)?$")>;
-def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "LPTEA$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "LRA(Y|G)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "STRAG$")>;
-def : InstRW<[WLat30, MCD], (instregex "LURA(G)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "STUR(A|G)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TPROT$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Memory-move Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat4LSU, FXa2, FXb, LSU5, GroupAlone2], (instregex "MVC(K|P|S)$")>;
-def : InstRW<[WLat1, FXa, LSU5, GroupAlone2], (instregex "MVC(S|D)K$")>;
-def : InstRW<[WLat30, MCD], (instregex "MVCOS$")>;
-def : InstRW<[WLat30, MCD], (instregex "MVPG$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Address-Space Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "LASP$")>;
-def : InstRW<[WLat1, LSU, GroupAlone], (instregex "PALB$")>;
-def : InstRW<[WLat30, MCD], (instregex "PC$")>;
-def : InstRW<[WLat30, MCD], (instregex "PR$")>;
-def : InstRW<[WLat30, MCD], (instregex "PT(I)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "RP$")>;
-def : InstRW<[WLat30, MCD], (instregex "BS(G|A)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TAR$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Linkage-Stack Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "BAKR$")>;
-def : InstRW<[WLat30, MCD], (instregex "EREG(G)?$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "(E|M)STA$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Time-Related Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "PTFF$")>;
-def : InstRW<[WLat30, MCD], (instregex "SCK(PF|C)?$")>;
-def : InstRW<[WLat1, LSU2, GroupAlone], (instregex "SPT$")>;
-def : InstRW<[WLat15, LSU3, FXa2, FXb, GroupAlone2], (instregex "STCK(F)?$")>;
-def : InstRW<[WLat20, LSU4, FXa2, FXb2, GroupAlone3], (instregex "STCKE$")>;
-def : InstRW<[WLat30, MCD], (instregex "STCKC$")>;
-def : InstRW<[WLat1, LSU2, FXb, Cracked], (instregex "STPT$")>;
-
-//===----------------------------------------------------------------------===//
-// System: CPU-Related Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "STAP$")>;
-def : InstRW<[WLat30, MCD], (instregex "STIDP$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "STSI$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "STFL(E)?$")>;
-def : InstRW<[WLat30, MCD], (instregex "ECAG$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "ECTG$")>;
-def : InstRW<[WLat30, MCD], (instregex "PTF$")>;
-def : InstRW<[WLat30, MCD], (instregex "PCKMO$")>;
-
-//===----------------------------------------------------------------------===//
-// System: Miscellaneous Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "SVC$")>;
-def : InstRW<[WLat1, FXb, GroupAlone], (instregex "MC$")>;
-def : InstRW<[WLat30, MCD], (instregex "DIAG$")>;
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "TRAC(E|G)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TRAP(2|4)$")>;
-def : InstRW<[WLat30, MCD], (instregex "SIG(P|A)$")>;
-def : InstRW<[WLat30, MCD], (instregex "SIE$")>;
-
-//===----------------------------------------------------------------------===//
-// System: CPU-Measurement Facility Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "LPP$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "ECPGA$")>;
-def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
-def : InstRW<[WLat30, MCD], (instregex "LCCTL$")>;
-def : InstRW<[WLat30, MCD], (instregex "L(P|S)CTL$")>;
-def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
-def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
-
-//===----------------------------------------------------------------------===//
-// System: I/O Instructions
-//===----------------------------------------------------------------------===//
-
-def : InstRW<[WLat30, MCD], (instregex "(C|H|R|X)SCH$")>;
-def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;
-def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;
-def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;
-def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
-def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
-def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
-
-}
-

Copied: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ15.td (from r372434, llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ15.td?p2=llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ15.td&p1=llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td&r1=372434&r2=372435&rev=372435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleArch13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ15.td Fri Sep 20 16:04:45 2019
@@ -1,4 +1,4 @@
-//-- SystemZScheduleArch13.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
+//-- SystemZScheduleZ15.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines the machine model for Arch13 to support instruction
+// This file defines the machine model for Z15 to support instruction
 // scheduling and other instruction cost heuristics.
 //
 // Pseudos expanded right after isel do not need to be modelled here.
 //
 //===----------------------------------------------------------------------===//
 
-def Arch13Model : SchedMachineModel {
+def Z15Model : SchedMachineModel {
 
     let UnsupportedFeatures = Arch13UnsupportedFeatures.List;
 
@@ -27,7 +27,7 @@ def Arch13Model : SchedMachineModel {
     let MispredictPenalty = 20;
 }
 
-let SchedModel = Arch13Model in  {
+let SchedModel = Z15Model in  {
 // These definitions need the SchedModel value. They could be put in a
 // subtarget common include file, but it seems the include system in Tablegen
 // currently (2016) rejects multiple includes of same file.
@@ -73,43 +73,43 @@ let NumMicroOps = 0 in {
 }
 
 // Execution units.
-def Arch13_FXaUnit     : ProcResource<2>;
-def Arch13_FXbUnit     : ProcResource<2>;
-def Arch13_LSUnit      : ProcResource<2>;
-def Arch13_VecUnit     : ProcResource<2>;
-def Arch13_VecFPdUnit  : ProcResource<2> { let BufferSize = 1; /* blocking */ }
-def Arch13_VBUnit      : ProcResource<2>;
-def Arch13_MCD         : ProcResource<1>;
+def Z15_FXaUnit     : ProcResource<2>;
+def Z15_FXbUnit     : ProcResource<2>;
+def Z15_LSUnit      : ProcResource<2>;
+def Z15_VecUnit     : ProcResource<2>;
+def Z15_VecFPdUnit  : ProcResource<2> { let BufferSize = 1; /* blocking */ }
+def Z15_VBUnit      : ProcResource<2>;
+def Z15_MCD         : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXa, [Arch13_FXaUnit]>;
-  def : WriteRes<FXb, [Arch13_FXbUnit]>;
-  def : WriteRes<LSU, [Arch13_LSUnit]>;
-  def : WriteRes<VecBF,  [Arch13_VecUnit]>;
-  def : WriteRes<VecDF,  [Arch13_VecUnit]>;
-  def : WriteRes<VecDFX, [Arch13_VecUnit]>;
-  def : WriteRes<VecMul,  [Arch13_VecUnit]>;
-  def : WriteRes<VecStr,  [Arch13_VecUnit]>;
-  def : WriteRes<VecXsPm, [Arch13_VecUnit]>;
+  def : WriteRes<FXa, [Z15_FXaUnit]>;
+  def : WriteRes<FXb, [Z15_FXbUnit]>;
+  def : WriteRes<LSU, [Z15_LSUnit]>;
+  def : WriteRes<VecBF,  [Z15_VecUnit]>;
+  def : WriteRes<VecDF,  [Z15_VecUnit]>;
+  def : WriteRes<VecDFX, [Z15_VecUnit]>;
+  def : WriteRes<VecMul,  [Z15_VecUnit]>;
+  def : WriteRes<VecStr,  [Z15_VecUnit]>;
+  def : WriteRes<VecXsPm, [Z15_VecUnit]>;
   foreach Num = 2-5 in { let ResourceCycles = [Num] in {
-    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Arch13_FXaUnit]>;
-    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Arch13_FXbUnit]>;
-    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Arch13_LSUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Arch13_VecUnit]>;
-    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Arch13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z15_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z15_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z15_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z15_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z15_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
   }}
 
-  def : WriteRes<VecFPd,  [Arch13_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<VecFPd,  [Z15_VecFPdUnit]> { let ResourceCycles = [30]; }
 
-  def : WriteRes<VBU,     [Arch13_VBUnit]>; // Virtual Branching Unit
+  def : WriteRes<VBU,     [Z15_VBUnit]>; // Virtual Branching Unit
 }
 
-def : WriteRes<MCD, [Arch13_MCD]> { let NumMicroOps = 3;
+def : WriteRes<MCD, [Z15_MCD]> { let NumMicroOps = 3;
                                     let BeginGroup  = 1;
                                     let EndGroup    = 1; }
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp Fri Sep 20 16:04:45 2019
@@ -707,7 +707,7 @@ int SystemZTTIImpl::getCastInstrCost(uns
       // TODO: Fix base implementation which could simplify things a bit here
       // (seems to miss on differentiating on scalar/vector types).
 
-      // Only 64 bit vector conversions are natively supported before arch13.
+      // Only 64 bit vector conversions are natively supported before z15.
       if (DstScalarBits == 64 || ST->hasVectorEnhancements2()) {
         if (SrcScalarBits == DstScalarBits)
           return NumDstVectors;

Modified: llvm/trunk/test/Analysis/CostModel/SystemZ/fp-cast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/SystemZ/fp-cast.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/SystemZ/fp-cast.ll (original)
+++ llvm/trunk/test/Analysis/CostModel/SystemZ/fp-cast.ll Fri Sep 20 16:04:45 2019
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 \
 ; RUN:  | FileCheck %s -check-prefixes=CHECK,Z13
-; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=arch13 \
-; RUN:  | FileCheck %s -check-prefixes=CHECK,AR13
+; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z15 \
+; RUN:  | FileCheck %s -check-prefixes=CHECK,Z15
 ;
 ; Note: The scalarized vector instructions costs are not including any
 ; extracts, due to the undef operands.
@@ -118,7 +118,7 @@ define void @fptosi() {
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v19 = fptosi <2 x double> undef to <2 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 5 for instruction:   %v20 = fptosi <2 x float> undef to <2 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 12 for instruction:   %v21 = fptosi <2 x float> undef to <2 x i32>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v21 = fptosi <2 x float> undef to <2 x i32>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v21 = fptosi <2 x float> undef to <2 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v22 = fptosi <2 x float> undef to <2 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v23 = fptosi <2 x float> undef to <2 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v24 = fptosi <4 x fp128> undef to <4 x i64>
@@ -131,7 +131,7 @@ define void @fptosi() {
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v31 = fptosi <4 x double> undef to <4 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %v32 = fptosi <4 x float> undef to <4 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 12 for instruction:   %v33 = fptosi <4 x float> undef to <4 x i32>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v33 = fptosi <4 x float> undef to <4 x i32>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v33 = fptosi <4 x float> undef to <4 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v34 = fptosi <4 x float> undef to <4 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v35 = fptosi <4 x float> undef to <4 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v36 = fptosi <8 x fp128> undef to <8 x i64>
@@ -144,7 +144,7 @@ define void @fptosi() {
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %v43 = fptosi <8 x double> undef to <8 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %v44 = fptosi <8 x float> undef to <8 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 24 for instruction:   %v45 = fptosi <8 x float> undef to <8 x i32>
-; AR13:  Cost Model: Found an estimated cost of 2 for instruction:   %v45 = fptosi <8 x float> undef to <8 x i32>
+; Z15:   Cost Model: Found an estimated cost of 2 for instruction:   %v45 = fptosi <8 x float> undef to <8 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %v46 = fptosi <8 x float> undef to <8 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %v47 = fptosi <8 x float> undef to <8 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 8 for instruction:   %v48 = fptosi <16 x double> undef to <16 x i64>
@@ -153,7 +153,7 @@ define void @fptosi() {
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %v51 = fptosi <16 x double> undef to <16 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %v52 = fptosi <16 x float> undef to <16 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 48 for instruction:   %v53 = fptosi <16 x float> undef to <16 x i32>
-; AR13:  Cost Model: Found an estimated cost of 4 for instruction:   %v53 = fptosi <16 x float> undef to <16 x i32>
+; Z15:   Cost Model: Found an estimated cost of 4 for instruction:   %v53 = fptosi <16 x float> undef to <16 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %v54 = fptosi <16 x float> undef to <16 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %v55 = fptosi <16 x float> undef to <16 x i8>
 
@@ -241,7 +241,7 @@ define void @fptoui() {
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v19 = fptoui <2 x double> undef to <2 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 5 for instruction:   %v20 = fptoui <2 x float> undef to <2 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 12 for instruction:   %v21 = fptoui <2 x float> undef to <2 x i32>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v21 = fptoui <2 x float> undef to <2 x i32>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v21 = fptoui <2 x float> undef to <2 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v22 = fptoui <2 x float> undef to <2 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v23 = fptoui <2 x float> undef to <2 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %v24 = fptoui <4 x fp128> undef to <4 x i64>
@@ -254,7 +254,7 @@ define void @fptoui() {
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v31 = fptoui <4 x double> undef to <4 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %v32 = fptoui <4 x float> undef to <4 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 12 for instruction:   %v33 = fptoui <4 x float> undef to <4 x i32>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v33 = fptoui <4 x float> undef to <4 x i32>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v33 = fptoui <4 x float> undef to <4 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v34 = fptoui <4 x float> undef to <4 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v35 = fptoui <4 x float> undef to <4 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %v36 = fptoui <8 x fp128> undef to <8 x i64>
@@ -267,7 +267,7 @@ define void @fptoui() {
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %v43 = fptoui <8 x double> undef to <8 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %v44 = fptoui <8 x float> undef to <8 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 24 for instruction:   %v45 = fptoui <8 x float> undef to <8 x i32>
-; AR13:  Cost Model: Found an estimated cost of 2 for instruction:   %v45 = fptoui <8 x float> undef to <8 x i32>
+; Z15:   Cost Model: Found an estimated cost of 2 for instruction:   %v45 = fptoui <8 x float> undef to <8 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %v46 = fptoui <8 x float> undef to <8 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %v47 = fptoui <8 x float> undef to <8 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 8 for instruction:   %v48 = fptoui <16 x double> undef to <16 x i64>
@@ -276,7 +276,7 @@ define void @fptoui() {
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %v51 = fptoui <16 x double> undef to <16 x i8>
 ; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %v52 = fptoui <16 x float> undef to <16 x i64>
 ; Z13:   Cost Model: Found an estimated cost of 48 for instruction:   %v53 = fptoui <16 x float> undef to <16 x i32>
-; AR13:  Cost Model: Found an estimated cost of 4 for instruction:   %v53 = fptoui <16 x float> undef to <16 x i32>
+; Z15:   Cost Model: Found an estimated cost of 4 for instruction:   %v53 = fptoui <16 x float> undef to <16 x i32>
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %v54 = fptoui <16 x float> undef to <16 x i16>
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %v55 = fptoui <16 x float> undef to <16 x i8>
 
@@ -391,7 +391,7 @@ define void @sitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 5 for instruction:   %v15 = sitofp <2 x i32> undef to <2 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 7 for instruction:   %v16 = sitofp <2 x i32> undef to <2 x double>
 ; Z13:   Cost Model: Found an estimated cost of 14 for instruction:   %v17 = sitofp <2 x i32> undef to <2 x float>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v17 = sitofp <2 x i32> undef to <2 x float>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v17 = sitofp <2 x i32> undef to <2 x float>
 ; CHECK: Cost Model: Found an estimated cost of 7 for instruction:   %v18 = sitofp <2 x i16> undef to <2 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 9 for instruction:   %v19 = sitofp <2 x i16> undef to <2 x double>
 ; CHECK: Cost Model: Found an estimated cost of 9 for instruction:   %v20 = sitofp <2 x i16> undef to <2 x float>
@@ -404,7 +404,7 @@ define void @sitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 9 for instruction:   %v27 = sitofp <4 x i32> undef to <4 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 13 for instruction:   %v28 = sitofp <4 x i32> undef to <4 x double>
 ; Z13:   Cost Model: Found an estimated cost of 13 for instruction:   %v29 = sitofp <4 x i32> undef to <4 x float>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v29 = sitofp <4 x i32> undef to <4 x float>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v29 = sitofp <4 x i32> undef to <4 x float>
 ; CHECK: Cost Model: Found an estimated cost of 13 for instruction:   %v30 = sitofp <4 x i16> undef to <4 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 17 for instruction:   %v31 = sitofp <4 x i16> undef to <4 x double>
 ; CHECK: Cost Model: Found an estimated cost of 17 for instruction:   %v32 = sitofp <4 x i16> undef to <4 x float>
@@ -417,7 +417,7 @@ define void @sitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 17 for instruction:   %v39 = sitofp <8 x i32> undef to <8 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 25 for instruction:   %v40 = sitofp <8 x i32> undef to <8 x double>
 ; Z13:   Cost Model: Found an estimated cost of 25 for instruction:   %v41 = sitofp <8 x i32> undef to <8 x float>
-; AR13:  Cost Model: Found an estimated cost of 2 for instruction:   %v41 = sitofp <8 x i32> undef to <8 x float>
+; Z15:   Cost Model: Found an estimated cost of 2 for instruction:   %v41 = sitofp <8 x i32> undef to <8 x float>
 ; CHECK: Cost Model: Found an estimated cost of 25 for instruction:   %v42 = sitofp <8 x i16> undef to <8 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 33 for instruction:   %v43 = sitofp <8 x i16> undef to <8 x double>
 ; CHECK: Cost Model: Found an estimated cost of 33 for instruction:   %v44 = sitofp <8 x i16> undef to <8 x float>
@@ -428,7 +428,7 @@ define void @sitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 49 for instruction:   %v49 = sitofp <16 x i64> undef to <16 x float>
 ; CHECK: Cost Model: Found an estimated cost of 49 for instruction:   %v50 = sitofp <16 x i32> undef to <16 x double>
 ; Z13:   Cost Model: Found an estimated cost of 49 for instruction:   %v51 = sitofp <16 x i32> undef to <16 x float>
-; AR13:  Cost Model: Found an estimated cost of 4 for instruction:   %v51 = sitofp <16 x i32> undef to <16 x float>
+; Z15:   Cost Model: Found an estimated cost of 4 for instruction:   %v51 = sitofp <16 x i32> undef to <16 x float>
 ; CHECK: Cost Model: Found an estimated cost of 65 for instruction:   %v52 = sitofp <16 x i16> undef to <16 x double>
 ; CHECK: Cost Model: Found an estimated cost of 65 for instruction:   %v53 = sitofp <16 x i16> undef to <16 x float>
 ; CHECK: Cost Model: Found an estimated cost of 65 for instruction:   %v54 = sitofp <16 x i8> undef to <16 x double>
@@ -513,7 +513,7 @@ define void @uitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 5 for instruction:   %v15 = uitofp <2 x i32> undef to <2 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 7 for instruction:   %v16 = uitofp <2 x i32> undef to <2 x double>
 ; Z13:   Cost Model: Found an estimated cost of 14 for instruction:   %v17 = uitofp <2 x i32> undef to <2 x float>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v17 = uitofp <2 x i32> undef to <2 x float>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v17 = uitofp <2 x i32> undef to <2 x float>
 ; CHECK: Cost Model: Found an estimated cost of 7 for instruction:   %v18 = uitofp <2 x i16> undef to <2 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 9 for instruction:   %v19 = uitofp <2 x i16> undef to <2 x double>
 ; CHECK: Cost Model: Found an estimated cost of 9 for instruction:   %v20 = uitofp <2 x i16> undef to <2 x float>
@@ -526,7 +526,7 @@ define void @uitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 9 for instruction:   %v27 = uitofp <4 x i32> undef to <4 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 13 for instruction:   %v28 = uitofp <4 x i32> undef to <4 x double>
 ; Z13:   Cost Model: Found an estimated cost of 13 for instruction:   %v29 = uitofp <4 x i32> undef to <4 x float>
-; AR13:  Cost Model: Found an estimated cost of 1 for instruction:   %v29 = uitofp <4 x i32> undef to <4 x float>
+; Z15:   Cost Model: Found an estimated cost of 1 for instruction:   %v29 = uitofp <4 x i32> undef to <4 x float>
 ; CHECK: Cost Model: Found an estimated cost of 13 for instruction:   %v30 = uitofp <4 x i16> undef to <4 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 17 for instruction:   %v31 = uitofp <4 x i16> undef to <4 x double>
 ; CHECK: Cost Model: Found an estimated cost of 17 for instruction:   %v32 = uitofp <4 x i16> undef to <4 x float>
@@ -539,7 +539,7 @@ define void @uitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 17 for instruction:   %v39 = uitofp <8 x i32> undef to <8 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 25 for instruction:   %v40 = uitofp <8 x i32> undef to <8 x double>
 ; Z13:   Cost Model: Found an estimated cost of 25 for instruction:   %v41 = uitofp <8 x i32> undef to <8 x float>
-; AR13:  Cost Model: Found an estimated cost of 2 for instruction:   %v41 = uitofp <8 x i32> undef to <8 x float>
+; Z15:   Cost Model: Found an estimated cost of 2 for instruction:   %v41 = uitofp <8 x i32> undef to <8 x float>
 ; CHECK: Cost Model: Found an estimated cost of 25 for instruction:   %v42 = uitofp <8 x i16> undef to <8 x fp128>
 ; CHECK: Cost Model: Found an estimated cost of 33 for instruction:   %v43 = uitofp <8 x i16> undef to <8 x double>
 ; CHECK: Cost Model: Found an estimated cost of 33 for instruction:   %v44 = uitofp <8 x i16> undef to <8 x float>
@@ -550,7 +550,7 @@ define void @uitofp() {
 ; CHECK: Cost Model: Found an estimated cost of 49 for instruction:   %v49 = uitofp <16 x i64> undef to <16 x float>
 ; CHECK: Cost Model: Found an estimated cost of 49 for instruction:   %v50 = uitofp <16 x i32> undef to <16 x double>
 ; Z13:   Cost Model: Found an estimated cost of 49 for instruction:   %v51 = uitofp <16 x i32> undef to <16 x float>
-; AR13:  Cost Model: Found an estimated cost of 4 for instruction:   %v51 = uitofp <16 x i32> undef to <16 x float>
+; Z15:   Cost Model: Found an estimated cost of 4 for instruction:   %v51 = uitofp <16 x i32> undef to <16 x float>
 ; CHECK: Cost Model: Found an estimated cost of 65 for instruction:   %v52 = uitofp <16 x i16> undef to <16 x double>
 ; CHECK: Cost Model: Found an estimated cost of 65 for instruction:   %v53 = uitofp <16 x i16> undef to <16 x float>
 ; CHECK: Cost Model: Found an estimated cost of 65 for instruction:   %v54 = uitofp <16 x i8> undef to <16 x double>

Modified: llvm/trunk/test/Analysis/CostModel/SystemZ/intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/SystemZ/intrinsics.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/SystemZ/intrinsics.ll (original)
+++ llvm/trunk/test/Analysis/CostModel/SystemZ/intrinsics.ll Fri Sep 20 16:04:45 2019
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 \
 ; RUN:  | FileCheck %s -check-prefixes=CHECK,Z13
-; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=arch13 \
-; RUN:  | FileCheck %s -check-prefixes=CHECK,AR13
+; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z15 \
+; RUN:  | FileCheck %s -check-prefixes=CHECK,Z15
 
 define void @bswap_i64(i64 %arg, <2 x i64> %arg2) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'bswap_i64':
@@ -69,15 +69,15 @@ define void @bswap_i64_mem(i64* %src, i6
 define void @bswap_v2i64_mem(<2 x i64>* %src, <2 x i64> %arg, <2 x i64>* %dst) {
 ; CHECK:Printing analysis 'Cost Model Analysis' for function 'bswap_v2i64_mem':
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %Ld1 = load <2 x i64>, <2 x i64>* %src
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %Ld1 = load <2 x i64>, <2 x i64>* %src
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %Ld1 = load <2 x i64>, <2 x i64>* %src
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp1 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld1)
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp2 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %arg)
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   store <2 x i64> %swp2, <2 x i64>* %dst
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   store <2 x i64> %swp2, <2 x i64>* %dst
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   store <2 x i64> %swp2, <2 x i64>* %dst
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %Ld2 = load <2 x i64>, <2 x i64>* %src
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp3 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld2)
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   store <2 x i64> %swp3, <2 x i64>* %dst
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   store <2 x i64> %swp3, <2 x i64>* %dst
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   store <2 x i64> %swp3, <2 x i64>* %dst
 
   %Ld1  = load <2 x i64>, <2 x i64>* %src
   %swp1 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld1)
@@ -117,15 +117,15 @@ define void @bswap_i32_mem(i32* %src, i3
 define void @bswap_v4i32_mem(<4 x i32>* %src, <4 x i32> %arg, <4 x i32>* %dst) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'bswap_v4i32_mem':
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %Ld1 = load <4 x i32>, <4 x i32>* %src
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %Ld1 = load <4 x i32>, <4 x i32>* %src
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %Ld1 = load <4 x i32>, <4 x i32>* %src
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp1 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %Ld1)
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp2 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %arg)
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   store <4 x i32> %swp2, <4 x i32>* %dst
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   store <4 x i32> %swp2, <4 x i32>* %dst
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   store <4 x i32> %swp2, <4 x i32>* %dst
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %Ld2 = load <4 x i32>, <4 x i32>* %src
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp3 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %Ld2)
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   store <4 x i32> %swp3, <4 x i32>* %dst
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   store <4 x i32> %swp3, <4 x i32>* %dst
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   store <4 x i32> %swp3, <4 x i32>* %dst
 %Ld1  = load <4 x i32>, <4 x i32>* %src
   %swp1 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %Ld1)
 
@@ -164,15 +164,15 @@ define void @bswap_i16_mem(i16* %src, i1
 define void @bswap_v8i16_mem(<8 x i16>* %src, <8 x i16> %arg, <8 x i16>* %dst) {
 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'bswap_v8i16_mem':
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %Ld1 = load <8 x i16>, <8 x i16>* %src
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %Ld1 = load <8 x i16>, <8 x i16>* %src
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %Ld1 = load <8 x i16>, <8 x i16>* %src
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp1 = tail call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %Ld1)
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp2 = tail call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %arg)
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   store <8 x i16> %swp2, <8 x i16>* %dst
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   store <8 x i16> %swp2, <8 x i16>* %dst
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   store <8 x i16> %swp2, <8 x i16>* %dst
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %Ld2 = load <8 x i16>, <8 x i16>* %src
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %swp3 = tail call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %Ld2)
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   store <8 x i16> %swp3, <8 x i16>* %dst
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   store <8 x i16> %swp3, <8 x i16>* %dst
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   store <8 x i16> %swp3, <8 x i16>* %dst
 %Ld1  = load <8 x i16>, <8 x i16>* %src
   %swp1 = tail call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %Ld1)
 

Modified: llvm/trunk/test/Analysis/CostModel/SystemZ/logic-miscext3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/SystemZ/logic-miscext3.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/SystemZ/logic-miscext3.ll (original)
+++ llvm/trunk/test/Analysis/CostModel/SystemZ/logic-miscext3.ll Fri Sep 20 16:04:45 2019
@@ -1,25 +1,25 @@
 ; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 \
 ; RUN:  | FileCheck %s -check-prefixes=CHECK,Z13
-; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=arch13 \
-; RUN:  | FileCheck %s -check-prefixes=CHECK,AR13
+; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z15 \
+; RUN:  | FileCheck %s -check-prefixes=CHECK,Z15
 
 define void @fun0(i32 %a)  {
 ; CHECK-LABEL: Printing analysis 'Cost Model Analysis' for function 'fun0':
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c0 = xor i32 %l0, -1
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res0 = or i32 %a, %c0
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res0 = or i32 %a, %c0
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res0 = or i32 %a, %c0
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c1 = xor i32 %l1, -1
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res1 = and i32 %a, %c1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res1 = and i32 %a, %c1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res1 = and i32 %a, %c1
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c2 = and i32 %l2, %a
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res2 = xor i32 %c2, -1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res2 = xor i32 %c2, -1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res2 = xor i32 %c2, -1
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c3 = or i32 %l3, %a
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res3 = xor i32 %c3, -1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res3 = xor i32 %c3, -1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res3 = xor i32 %c3, -1
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c4 = xor i32 %l4, %a
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res4 = xor i32 %c4, -1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res4 = xor i32 %c4, -1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res4 = xor i32 %c4, -1
 
 entry:
   %l0 = load i32, i32* undef
@@ -54,19 +54,19 @@ define void @fun1(i64 %a)  {
 ; CHECK-LABEL: Printing analysis 'Cost Model Analysis' for function 'fun1':
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c0 = xor i64 %l0, -1
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res0 = or i64 %a, %c0
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res0 = or i64 %a, %c0
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res0 = or i64 %a, %c0
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c1 = xor i64 %l1, -1
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res1 = and i64 %a, %c1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res1 = and i64 %a, %c1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res1 = and i64 %a, %c1
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c2 = and i64 %l2, %a
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res2 = xor i64 %c2, -1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res2 = xor i64 %c2, -1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res2 = xor i64 %c2, -1
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c3 = or i64 %l3, %a
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res3 = xor i64 %c3, -1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res3 = xor i64 %c3, -1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res3 = xor i64 %c3, -1
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %c4 = xor i64 %l4, %a
 ; Z13:   Cost Model: Found an estimated cost of 1 for instruction:   %res4 = xor i64 %c4, -1
-; AR13:  Cost Model: Found an estimated cost of 0 for instruction:   %res4 = xor i64 %c4, -1
+; Z15:   Cost Model: Found an estimated cost of 0 for instruction:   %res4 = xor i64 %c4, -1
 entry:
   %l0 = load i64, i64* undef
   %c0 = xor i64 %l0, -1

Modified: llvm/trunk/test/CodeGen/SystemZ/cond-move-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-move-01.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-move-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-move-01.ll Fri Sep 20 16:04:45 2019
@@ -7,7 +7,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
 ;
 ; And again in the presence of the select instructions.
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s
 
 ; Test LOCR.
 define i32 @f1(i32 %a, i32 %b, i32 %limit) {

Modified: llvm/trunk/test/CodeGen/SystemZ/cond-move-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-move-02.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-move-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-move-02.ll Fri Sep 20 16:04:45 2019
@@ -4,7 +4,7 @@
 ;
 ; Run the test again to make sure it still works the same even
 ; in the presence of the select instructions.
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s
 
 
 define i32 @f1(i32 %x) {

Modified: llvm/trunk/test/CodeGen/SystemZ/cond-move-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-move-03.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-move-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-move-03.ll Fri Sep 20 16:04:45 2019
@@ -6,7 +6,7 @@
 ;
 ; Run the test again to make sure it still works the same even
 ; in the presence of the select instructions.
-; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=arch13 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z15 \
 ; RUN:   -no-integrated-as | FileCheck %s
 
 define void @f1(i32 %limit) {

Modified: llvm/trunk/test/CodeGen/SystemZ/cond-move-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-move-06.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-move-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-move-06.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test SELR and SELGR.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 -verify-machineinstrs | FileCheck %s
 
 ; Test SELR.
 define i32 @f1(i32 %limit, i32 %a, i32 %b) {

Modified: llvm/trunk/test/CodeGen/SystemZ/cond-move-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-move-07.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-move-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-move-07.ll Fri Sep 20 16:04:45 2019
@@ -1,7 +1,7 @@
 ; Test SELFHR.
 ; See comments in asm-18.ll about testing high-word operations.
 ;
-; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=arch13 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z15 \
 ; RUN:   -no-integrated-as | FileCheck %s
 
 define void @f1(i32 %limit) {

Modified: llvm/trunk/test/CodeGen/SystemZ/cond-move-08.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/cond-move-08.mir?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/cond-move-08.mir (original)
+++ llvm/trunk/test/CodeGen/SystemZ/cond-move-08.mir Fri Sep 20 16:04:45 2019
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=s390x-linux-gnu -mcpu=arch13 -start-before=greedy %s -o - \
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -start-before=greedy %s -o - \
 # RUN:   | FileCheck %s
 #
 # Test that regalloc manages (via regalloc hints) to avoid a LOCRMux jump
@@ -73,7 +73,7 @@
   ; Function Attrs: nounwind
   declare void @llvm.stackprotector(i8*, i8**) #1
 
-  attributes #0 = { "target-cpu"="arch13" }
+  attributes #0 = { "target-cpu"="z15" }
   attributes #1 = { nounwind }
 
 ...

Modified: llvm/trunk/test/CodeGen/SystemZ/ctpop-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/ctpop-02.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/ctpop-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/ctpop-02.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
-; Test population-count instruction on arch13
+; Test population-count instruction on z15
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare i32 @llvm.ctpop.i32(i32 %a)
 declare i64 @llvm.ctpop.i64(i64 %a)

Modified: llvm/trunk/test/CodeGen/SystemZ/not-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/not-01.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/not-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/not-01.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
-; Combined logical operations involving complement on arch13
+; Combined logical operations involving complement on z15
 ;
-; RUN: llc -mcpu=arch13 < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; And-with-complement 32-bit.
 define i32 @f1(i32 %dummy, i32 %a, i32 %b) {

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-01.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-01.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test loads of byte-swapped vector elements.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
 declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-02.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-02.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test stores of byte-swapped vector elements.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
 declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-03.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-03.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test vector insertion of byte-swapped memory values.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-04.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-04.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-04.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-04.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test vector extraction of byte-swapped value to memory.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-05.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-05.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-05.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-05.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test vector insertions of byte-swapped memory values into 0.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-06.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-06.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-06.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-06.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test insertions of byte-swapped memory values into a nonzero index of an undef.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-bswap-07.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-bswap-07.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-bswap-07.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-bswap-07.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test replications of a byte-swapped scalar memory value.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-conv-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-conv-03.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-conv-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-conv-03.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
-; Test conversions between integer and float elements on arch13.
+; Test conversions between integer and float elements on z15.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 ; Test conversion of f32s to signed i32s.
 define <4 x i32> @f1(<4 x float> %floats) {

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-eswap-01.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-eswap-01.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-eswap-01.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-eswap-01.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test loads of byte-swapped vector elements.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 ; Test v16i8 loads.
 define <16 x i8> @f1(<16 x i8> *%ptr) {

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-eswap-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-eswap-02.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-eswap-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-eswap-02.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
 ; Test stores of element-swapped vector elements.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 ; Test v16i8 stores.
 define void @f1(<16 x i8> %val, <16 x i8> *%ptr) {

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-03.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics-03.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
-; Test vector intrinsics added with arch13.
+; Test vector intrinsics added with z15.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 declare <16 x i8> @llvm.s390.vsld(<16 x i8>, <16 x i8>, i32)
 declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32)

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-strict-conv-03.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-strict-conv-03.ll?rev=372435&r1=372434&r2=372435&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-strict-conv-03.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-strict-conv-03.ll Fri Sep 20 16:04:45 2019
@@ -1,6 +1,6 @@
-; Test strict conversions between integer and float elements on arch13.
+; Test strict conversions between integer and float elements on z15.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
 
 ; FIXME: llvm.experimental.constrained.[su]itofp does not yet exist
 

Removed: llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt?rev=372434&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt (removed)
@@ -1,1479 +0,0 @@
-# Test arch13 instructions that don't have PC-relative operands.
-# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=arch13 \
-# RUN:   | FileCheck %s
-
-# CHECK: dfltcc %r2, %r2, %r2
-0xb9 0x39 0x20 0x22
-
-# CHECK: dfltcc %r2, %r8, %r15
-0xb9 0x39 0xf0 0x28
-
-# CHECK: dfltcc %r14, %r8, %r2
-0xb9 0x39 0x20 0xe8
-
-# CHECK: dfltcc %r6, %r8, %r10
-0xb9 0x39 0xa0 0x68
-
-# CHECK: kdsa %r0, %r2
-0xb9 0x3a 0x00 0x02
-
-# CHECK: kdsa %r0, %r14
-0xb9 0x3a 0x00 0x0e
-
-# CHECK: kdsa %r15, %r2
-0xb9 0x3a 0x00 0xf2
-
-# CHECK: kdsa %r7, %r10
-0xb9 0x3a 0x00 0x7a
-
-# CHECK: mvcrl 0, 0
-0xe5 0x0a 0x00 0x00 0x00 0x00
-
-# CHECK: mvcrl 0(%r1), 0(%r2)
-0xe5 0x0a 0x10 0x00 0x20 0x00
-
-# CHECK: mvcrl 160(%r1), 320(%r15)
-0xe5 0x0a 0x10 0xa0 0xf1 0x40
-
-# CHECK: mvcrl 0(%r1), 4095
-0xe5 0x0a 0x10 0x00 0x0f 0xff
-
-# CHECK: mvcrl 0(%r1), 4095(%r2)
-0xe5 0x0a 0x10 0x00 0x2f 0xff
-
-# CHECK: mvcrl 0(%r1), 4095(%r15)
-0xe5 0x0a 0x10 0x00 0xff 0xff
-
-# CHECK: mvcrl 0(%r1), 0
-0xe5 0x0a 0x10 0x00 0x00 0x00
-
-# CHECK: mvcrl 0(%r15), 0
-0xe5 0x0a 0xf0 0x00 0x00 0x00
-
-# CHECK: mvcrl 4095(%r1), 0
-0xe5 0x0a 0x1f 0xff 0x00 0x00
-
-# CHECK: mvcrl 4095(%r15), 0
-0xe5 0x0a 0xff 0xff 0x00 0x00
-
-# CHECK: ncgrk %r0, %r0, %r0
-0xb9 0xe5 0x00 0x00
-
-# CHECK: ncgrk %r0, %r0, %r15
-0xb9 0xe5 0xf0 0x00
-
-# CHECK: ncgrk %r0, %r15, %r0
-0xb9 0xe5 0x00 0x0f
-
-# CHECK: ncgrk %r15, %r0, %r0
-0xb9 0xe5 0x00 0xf0
-
-# CHECK: ncgrk %r7, %r8, %r9
-0xb9 0xe5 0x90 0x78
-
-# CHECK: ncrk %r0, %r0, %r0
-0xb9 0xf5 0x00 0x00
-
-# CHECK: ncrk %r0, %r0, %r15
-0xb9 0xf5 0xf0 0x00
-
-# CHECK: ncrk %r0, %r15, %r0
-0xb9 0xf5 0x00 0x0f
-
-# CHECK: ncrk %r15, %r0, %r0
-0xb9 0xf5 0x00 0xf0
-
-# CHECK: ncrk %r7, %r8, %r9
-0xb9 0xf5 0x90 0x78
-
-# CHECK: nngrk %r0, %r0, %r0
-0xb9 0x64 0x00 0x00
-
-# CHECK: nngrk %r0, %r0, %r15
-0xb9 0x64 0xf0 0x00
-
-# CHECK: nngrk %r0, %r15, %r0
-0xb9 0x64 0x00 0x0f
-
-# CHECK: nngrk %r15, %r0, %r0
-0xb9 0x64 0x00 0xf0
-
-# CHECK: nngrk %r7, %r8, %r9
-0xb9 0x64 0x90 0x78
-
-# CHECK: nnrk %r0, %r0, %r0
-0xb9 0x74 0x00 0x00
-
-# CHECK: nnrk %r0, %r0, %r15
-0xb9 0x74 0xf0 0x00
-
-# CHECK: nnrk %r0, %r15, %r0
-0xb9 0x74 0x00 0x0f
-
-# CHECK: nnrk %r15, %r0, %r0
-0xb9 0x74 0x00 0xf0
-
-# CHECK: nnrk %r7, %r8, %r9
-0xb9 0x74 0x90 0x78
-
-# CHECK: nogrk %r0, %r0, %r0
-0xb9 0x66 0x00 0x00
-
-# CHECK: nogrk %r0, %r0, %r15
-0xb9 0x66 0xf0 0x00
-
-# CHECK: nogrk %r0, %r15, %r0
-0xb9 0x66 0x00 0x0f
-
-# CHECK: nogrk %r15, %r0, %r0
-0xb9 0x66 0x00 0xf0
-
-# CHECK: nogrk %r7, %r8, %r9
-0xb9 0x66 0x90 0x78
-
-# CHECK: nork %r0, %r0, %r0
-0xb9 0x76 0x00 0x00
-
-# CHECK: nork %r0, %r0, %r15
-0xb9 0x76 0xf0 0x00
-
-# CHECK: nork %r0, %r15, %r0
-0xb9 0x76 0x00 0x0f
-
-# CHECK: nork %r15, %r0, %r0
-0xb9 0x76 0x00 0xf0
-
-# CHECK: nork %r7, %r8, %r9
-0xb9 0x76 0x90 0x78
-
-# CHECK: nxgrk %r0, %r0, %r0
-0xb9 0x67 0x00 0x00
-
-# CHECK: nxgrk %r0, %r0, %r15
-0xb9 0x67 0xf0 0x00
-
-# CHECK: nxgrk %r0, %r15, %r0
-0xb9 0x67 0x00 0x0f
-
-# CHECK: nxgrk %r15, %r0, %r0
-0xb9 0x67 0x00 0xf0
-
-# CHECK: nxgrk %r7, %r8, %r9
-0xb9 0x67 0x90 0x78
-
-# CHECK: nxrk %r0, %r0, %r0
-0xb9 0x77 0x00 0x00
-
-# CHECK: nxrk %r0, %r0, %r15
-0xb9 0x77 0xf0 0x00
-
-# CHECK: nxrk %r0, %r15, %r0
-0xb9 0x77 0x00 0x0f
-
-# CHECK: nxrk %r15, %r0, %r0
-0xb9 0x77 0x00 0xf0
-
-# CHECK: nxrk %r7, %r8, %r9
-0xb9 0x77 0x90 0x78
-
-# CHECK: ocgrk %r0, %r0, %r0
-0xb9 0x65 0x00 0x00
-
-# CHECK: ocgrk %r0, %r0, %r15
-0xb9 0x65 0xf0 0x00
-
-# CHECK: ocgrk %r0, %r15, %r0
-0xb9 0x65 0x00 0x0f
-
-# CHECK: ocgrk %r15, %r0, %r0
-0xb9 0x65 0x00 0xf0
-
-# CHECK: ocgrk %r7, %r8, %r9
-0xb9 0x65 0x90 0x78
-
-# CHECK: ocrk %r0, %r0, %r0
-0xb9 0x75 0x00 0x00
-
-# CHECK: ocrk %r0, %r0, %r15
-0xb9 0x75 0xf0 0x00
-
-# CHECK: ocrk %r0, %r15, %r0
-0xb9 0x75 0x00 0x0f
-
-# CHECK: ocrk %r15, %r0, %r0
-0xb9 0x75 0x00 0xf0
-
-# CHECK: ocrk %r7, %r8, %r9
-0xb9 0x75 0x90 0x78
-
-# CHECK: popcnt %r0, %r0
-0xb9 0xe1 0x00 0x00
-
-# CHECK: popcnt %r0, %r15
-0xb9 0xe1 0x00 0x0f
-
-# CHECK: popcnt %r14, %r0
-0xb9 0xe1 0x00 0xe0
-
-# CHECK: popcnt %r6, %r8
-0xb9 0xe1 0x00 0x68
-
-# CHECK: popcnt %r4, %r13, 1
-0xb9 0xe1 0x10 0x4d
-
-# CHECK: popcnt %r4, %r13, 15
-0xb9 0xe1 0xf0 0x4d
-
-# CHECK: selgr %r0, %r0, %r0, 0
-0xb9 0xe3 0x00 0x00
-
-# CHECK: selgr %r0, %r0, %r0, 15
-0xb9 0xe3 0x0f 0x00
-
-# CHECK: selgr %r0, %r0, %r15, 0
-0xb9 0xe3 0xf0 0x00
-
-# CHECK: selgr %r0, %r15, %r0, 0
-0xb9 0xe3 0x00 0x0f
-
-# CHECK: selgr %r15, %r0, %r0, 0
-0xb9 0xe3 0x00 0xf0
-
-# CHECK: selgro %r1, %r2, %r3
-0xb9 0xe3 0x31 0x12
-
-# CHECK: selgrh %r1, %r2, %r3
-0xb9 0xe3 0x32 0x12
-
-# CHECK: selgrnle %r1, %r2, %r3
-0xb9 0xe3 0x33 0x12
-
-# CHECK: selgrl %r1, %r2, %r3
-0xb9 0xe3 0x34 0x12
-
-# CHECK: selgrnhe %r1, %r2, %r3
-0xb9 0xe3 0x35 0x12
-
-# CHECK: selgrlh %r1, %r2, %r3
-0xb9 0xe3 0x36 0x12
-
-# CHECK: selgrne %r1, %r2, %r3
-0xb9 0xe3 0x37 0x12
-
-# CHECK: selgre %r1, %r2, %r3
-0xb9 0xe3 0x38 0x12
-
-# CHECK: selgrnlh %r1, %r2, %r3
-0xb9 0xe3 0x39 0x12
-
-# CHECK: selgrhe %r1, %r2, %r3
-0xb9 0xe3 0x3a 0x12
-
-# CHECK: selgrnl %r1, %r2, %r3
-0xb9 0xe3 0x3b 0x12
-
-# CHECK: selgrle %r1, %r2, %r3
-0xb9 0xe3 0x3c 0x12
-
-# CHECK: selgrnh %r1, %r2, %r3
-0xb9 0xe3 0x3d 0x12
-
-# CHECK: selgrno %r1, %r2, %r3
-0xb9 0xe3 0x3e 0x12
-
-# CHECK: selfhr %r0, %r0, %r0, 0
-0xb9 0xc0 0x00 0x00
-
-# CHECK: selfhr %r0, %r0, %r0, 15
-0xb9 0xc0 0x0f 0x00
-
-# CHECK: selfhr %r0, %r0, %r15, 0
-0xb9 0xc0 0xf0 0x00
-
-# CHECK: selfhr %r0, %r15, %r0, 0
-0xb9 0xc0 0x00 0x0f
-
-# CHECK: selfhr %r15, %r0, %r0, 0
-0xb9 0xc0 0x00 0xf0
-
-# CHECK: selfhro %r1, %r2, %r3
-0xb9 0xc0 0x31 0x12
-
-# CHECK: selfhrh %r1, %r2, %r3
-0xb9 0xc0 0x32 0x12
-
-# CHECK: selfhrnle %r1, %r2, %r3
-0xb9 0xc0 0x33 0x12
-
-# CHECK: selfhrl %r1, %r2, %r3
-0xb9 0xc0 0x34 0x12
-
-# CHECK: selfhrnhe %r1, %r2, %r3
-0xb9 0xc0 0x35 0x12
-
-# CHECK: selfhrlh %r1, %r2, %r3
-0xb9 0xc0 0x36 0x12
-
-# CHECK: selfhrne %r1, %r2, %r3
-0xb9 0xc0 0x37 0x12
-
-# CHECK: selfhre %r1, %r2, %r3
-0xb9 0xc0 0x38 0x12
-
-# CHECK: selfhrnlh %r1, %r2, %r3
-0xb9 0xc0 0x39 0x12
-
-# CHECK: selfhrhe %r1, %r2, %r3
-0xb9 0xc0 0x3a 0x12
-
-# CHECK: selfhrnl %r1, %r2, %r3
-0xb9 0xc0 0x3b 0x12
-
-# CHECK: selfhrle %r1, %r2, %r3
-0xb9 0xc0 0x3c 0x12
-
-# CHECK: selfhrnh %r1, %r2, %r3
-0xb9 0xc0 0x3d 0x12
-
-# CHECK: selfhrno %r1, %r2, %r3
-0xb9 0xc0 0x3e 0x12
-
-# CHECK: selr %r0, %r0, %r0, 0
-0xb9 0xf0 0x00 0x00
-
-# CHECK: selr %r0, %r0, %r0, 15
-0xb9 0xf0 0x0f 0x00
-
-# CHECK: selr %r0, %r0, %r15, 0
-0xb9 0xf0 0xf0 0x00
-
-# CHECK: selr %r0, %r15, %r0, 0
-0xb9 0xf0 0x00 0x0f
-
-# CHECK: selr %r15, %r0, %r0, 0
-0xb9 0xf0 0x00 0xf0
-
-# CHECK: selro %r1, %r2, %r3
-0xb9 0xf0 0x31 0x12
-
-# CHECK: selrh %r1, %r2, %r3
-0xb9 0xf0 0x32 0x12
-
-# CHECK: selrnle %r1, %r2, %r3
-0xb9 0xf0 0x33 0x12
-
-# CHECK: selrl %r1, %r2, %r3
-0xb9 0xf0 0x34 0x12
-
-# CHECK: selrnhe %r1, %r2, %r3
-0xb9 0xf0 0x35 0x12
-
-# CHECK: selrlh %r1, %r2, %r3
-0xb9 0xf0 0x36 0x12
-
-# CHECK: selrne %r1, %r2, %r3
-0xb9 0xf0 0x37 0x12
-
-# CHECK: selre %r1, %r2, %r3
-0xb9 0xf0 0x38 0x12
-
-# CHECK: selrnlh %r1, %r2, %r3
-0xb9 0xf0 0x39 0x12
-
-# CHECK: selrhe %r1, %r2, %r3
-0xb9 0xf0 0x3a 0x12
-
-# CHECK: selrnl %r1, %r2, %r3
-0xb9 0xf0 0x3b 0x12
-
-# CHECK: selrle %r1, %r2, %r3
-0xb9 0xf0 0x3c 0x12
-
-# CHECK: selrnh %r1, %r2, %r3
-0xb9 0xf0 0x3d 0x12
-
-# CHECK: selrno %r1, %r2, %r3
-0xb9 0xf0 0x3e 0x12
-
-# CHECK: sortl %r2, %r2
-0xb9 0x38 0x00 0x22
-
-# CHECK: sortl %r2, %r14
-0xb9 0x38 0x00 0x2e
-
-# CHECK: sortl %r14, %r2
-0xb9 0x38 0x00 0xe2
-
-# CHECK: sortl %r6, %r10
-0xb9 0x38 0x00 0x6a
-
-# CHECK: vcefb %v0, %v0, 0, 0
-0xe7 0x00 0x00 0x00 0x20 0xc3
-
-# CHECK: vcefb %v0, %v0, 0, 15
-0xe7 0x00 0x00 0xf0 0x20 0xc3
-
-# CHECK: vcefb %v0, %v0, 4, 0
-0xe7 0x00 0x00 0x04 0x20 0xc3
-
-# CHECK: vcefb %v0, %v31, 0, 0
-0xe7 0x0f 0x00 0x00 0x24 0xc3
-
-# CHECK: vcefb %v31, %v0, 0, 0
-0xe7 0xf0 0x00 0x00 0x28 0xc3
-
-# CHECK: vcefb %v14, %v17, 4, 10
-0xe7 0xe1 0x00 0xa4 0x24 0xc3
-
-# CHECK: vcelfb %v0, %v0, 0, 0
-0xe7 0x00 0x00 0x00 0x20 0xc1
-
-# CHECK: vcelfb %v0, %v0, 0, 15
-0xe7 0x00 0x00 0xf0 0x20 0xc1
-
-# CHECK: vcelfb %v0, %v0, 4, 0
-0xe7 0x00 0x00 0x04 0x20 0xc1
-
-# CHECK: vcelfb %v0, %v31, 0, 0
-0xe7 0x0f 0x00 0x00 0x24 0xc1
-
-# CHECK: vcelfb %v31, %v0, 0, 0
-0xe7 0xf0 0x00 0x00 0x28 0xc1
-
-# CHECK: vcelfb %v14, %v17, 4, 10
-0xe7 0xe1 0x00 0xa4 0x24 0xc1
-
-# CHECK: vcfeb %v0, %v0, 0, 0
-0xe7 0x00 0x00 0x00 0x20 0xc2
-
-# CHECK: vcfeb %v0, %v0, 0, 15
-0xe7 0x00 0x00 0xf0 0x20 0xc2
-
-# CHECK: vcfeb %v0, %v0, 4, 0
-0xe7 0x00 0x00 0x04 0x20 0xc2
-
-# CHECK: vcfeb %v0, %v31, 0, 0
-0xe7 0x0f 0x00 0x00 0x24 0xc2
-
-# CHECK: vcfeb %v31, %v0, 0, 0
-0xe7 0xf0 0x00 0x00 0x28 0xc2
-
-# CHECK: vcfeb %v14, %v17, 4, 10
-0xe7 0xe1 0x00 0xa4 0x24 0xc2
-
-# CHECK: vclfeb %v0, %v0, 0, 0
-0xe7 0x00 0x00 0x00 0x20 0xc0
-
-# CHECK: vclfeb %v0, %v0, 0, 15
-0xe7 0x00 0x00 0xf0 0x20 0xc0
-
-# CHECK: vclfeb %v0, %v0, 4, 0
-0xe7 0x00 0x00 0x04 0x20 0xc0
-
-# CHECK: vclfeb %v0, %v31, 0, 0
-0xe7 0x0f 0x00 0x00 0x24 0xc0
-
-# CHECK: vclfeb %v31, %v0, 0, 0
-0xe7 0xf0 0x00 0x00 0x28 0xc0
-
-# CHECK: vclfeb %v14, %v17, 4, 10
-0xe7 0xe1 0x00 0xa4 0x24 0xc0
-
-# CHECK: vcvb %r0, %v0, 0, 15
-0xe6 0x00 0x00 0x0f 0x00 0x50
-
-# CHECK: vcvb %r3, %v18, 4, 6
-0xe6 0x32 0x00 0x46 0x04 0x50
-
-# CHECK: vcvbg %r0, %v0, 0, 15
-0xe6 0x00 0x00 0x0f 0x00 0x52
-
-# CHECK: vcvbg %r3, %v18, 4, 6
-0xe6 0x32 0x00 0x46 0x04 0x52
-
-# CHECK: vlbr %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x06
-
-# CHECK: vlbr %v0, 0, 15
-0xe6 0x00 0x00 0x00 0xf0 0x06
-
-# CHECK: vlbr %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x06
-
-# CHECK: vlbr %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x06
-
-# CHECK: vlbr %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x06
-
-# CHECK: vlbr %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x06
-
-# CHECK: vlbr %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x06
-
-# CHECK: vlbr %v18, 1383(%r3,%r4), 11
-0xe6 0x23 0x45 0x67 0xb8 0x06
-
-# CHECK: vlbrf %v0, 0
-0xe6 0x00 0x00 0x00 0x20 0x06
-
-# CHECK: vlbrf %v0, 4095
-0xe6 0x00 0x0f 0xff 0x20 0x06
-
-# CHECK: vlbrf %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x20 0x06
-
-# CHECK: vlbrf %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x20 0x06
-
-# CHECK: vlbrf %v15, 0
-0xe6 0xf0 0x00 0x00 0x20 0x06
-
-# CHECK: vlbrf %v31, 0
-0xe6 0xf0 0x00 0x00 0x28 0x06
-
-# CHECK: vlbrf %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x28 0x06
-
-# CHECK: vlbrg %v0, 0
-0xe6 0x00 0x00 0x00 0x30 0x06
-
-# CHECK: vlbrg %v0, 4095
-0xe6 0x00 0x0f 0xff 0x30 0x06
-
-# CHECK: vlbrg %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x30 0x06
-
-# CHECK: vlbrg %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x30 0x06
-
-# CHECK: vlbrg %v15, 0
-0xe6 0xf0 0x00 0x00 0x30 0x06
-
-# CHECK: vlbrg %v31, 0
-0xe6 0xf0 0x00 0x00 0x38 0x06
-
-# CHECK: vlbrg %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x38 0x06
-
-# CHECK: vlbrh %v0, 0
-0xe6 0x00 0x00 0x00 0x10 0x06
-
-# CHECK: vlbrh %v0, 4095
-0xe6 0x00 0x0f 0xff 0x10 0x06
-
-# CHECK: vlbrh %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x10 0x06
-
-# CHECK: vlbrh %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x10 0x06
-
-# CHECK: vlbrh %v15, 0
-0xe6 0xf0 0x00 0x00 0x10 0x06
-
-# CHECK: vlbrh %v31, 0
-0xe6 0xf0 0x00 0x00 0x18 0x06
-
-# CHECK: vlbrh %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x18 0x06
-
-# CHECK: vlbrq %v0, 0
-0xe6 0x00 0x00 0x00 0x40 0x06
-
-# CHECK: vlbrq %v0, 4095
-0xe6 0x00 0x0f 0xff 0x40 0x06
-
-# CHECK: vlbrq %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x40 0x06
-
-# CHECK: vlbrq %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x40 0x06
-
-# CHECK: vlbrq %v15, 0
-0xe6 0xf0 0x00 0x00 0x40 0x06
-
-# CHECK: vlbrq %v31, 0
-0xe6 0xf0 0x00 0x00 0x48 0x06
-
-# CHECK: vlbrq %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x48 0x06
-
-# CHECK: vlbrrep %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x05
-
-# CHECK: vlbrrep %v0, 0, 15
-0xe6 0x00 0x00 0x00 0xf0 0x05
-
-# CHECK: vlbrrep %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x05
-
-# CHECK: vlbrrep %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x05
-
-# CHECK: vlbrrep %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x05
-
-# CHECK: vlbrrep %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x05
-
-# CHECK: vlbrrep %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x05
-
-# CHECK: vlbrrep %v18, 1383(%r3,%r4), 11
-0xe6 0x23 0x45 0x67 0xb8 0x05
-
-# CHECK: vlbrrepf %v0, 0
-0xe6 0x00 0x00 0x00 0x20 0x05
-
-# CHECK: vlbrrepf %v0, 4095
-0xe6 0x00 0x0f 0xff 0x20 0x05
-
-# CHECK: vlbrrepf %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x20 0x05
-
-# CHECK: vlbrrepf %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x20 0x05
-
-# CHECK: vlbrrepf %v15, 0
-0xe6 0xf0 0x00 0x00 0x20 0x05
-
-# CHECK: vlbrrepf %v31, 0
-0xe6 0xf0 0x00 0x00 0x28 0x05
-
-# CHECK: vlbrrepf %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x28 0x05
-
-# CHECK: vlbrrepg %v0, 0
-0xe6 0x00 0x00 0x00 0x30 0x05
-
-# CHECK: vlbrrepg %v0, 4095
-0xe6 0x00 0x0f 0xff 0x30 0x05
-
-# CHECK: vlbrrepg %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x30 0x05
-
-# CHECK: vlbrrepg %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x30 0x05
-
-# CHECK: vlbrrepg %v15, 0
-0xe6 0xf0 0x00 0x00 0x30 0x05
-
-# CHECK: vlbrrepg %v31, 0
-0xe6 0xf0 0x00 0x00 0x38 0x05
-
-# CHECK: vlbrrepg %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x38 0x05
-
-# CHECK: vlbrreph %v0, 0
-0xe6 0x00 0x00 0x00 0x10 0x05
-
-# CHECK: vlbrreph %v0, 4095
-0xe6 0x00 0x0f 0xff 0x10 0x05
-
-# CHECK: vlbrreph %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x10 0x05
-
-# CHECK: vlbrreph %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x10 0x05
-
-# CHECK: vlbrreph %v15, 0
-0xe6 0xf0 0x00 0x00 0x10 0x05
-
-# CHECK: vlbrreph %v31, 0
-0xe6 0xf0 0x00 0x00 0x18 0x05
-
-# CHECK: vlbrreph %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x18 0x05
-
-# CHECK: vlebrf %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x03
-
-# CHECK: vlebrf %v0, 0, 3
-0xe6 0x00 0x00 0x00 0x30 0x03
-
-# CHECK: vlebrf %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x03
-
-# CHECK: vlebrf %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x03
-
-# CHECK: vlebrf %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x03
-
-# CHECK: vlebrf %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x03
-
-# CHECK: vlebrf %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x03
-
-# CHECK: vlebrf %v18, 1383(%r3,%r4), 2
-0xe6 0x23 0x45 0x67 0x28 0x03
-
-# CHECK: vlebrg %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x02
-
-# CHECK: vlebrg %v0, 0, 1
-0xe6 0x00 0x00 0x00 0x10 0x02
-
-# CHECK: vlebrg %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x02
-
-# CHECK: vlebrg %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x02
-
-# CHECK: vlebrg %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x02
-
-# CHECK: vlebrg %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x02
-
-# CHECK: vlebrg %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x02
-
-# CHECK: vlebrg %v18, 1383(%r3,%r4), 1
-0xe6 0x23 0x45 0x67 0x18 0x02
-
-# CHECK: vlebrh %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x01
-
-# CHECK: vlebrh %v0, 0, 7
-0xe6 0x00 0x00 0x00 0x70 0x01
-
-# CHECK: vlebrh %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x01
-
-# CHECK: vlebrh %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x01
-
-# CHECK: vlebrh %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x01
-
-# CHECK: vlebrh %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x01
-
-# CHECK: vlebrh %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x01
-
-# CHECK: vlebrh %v18, 1383(%r3,%r4), 4
-0xe6 0x23 0x45 0x67 0x48 0x01
-
-# CHECK: vler %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x07
-
-# CHECK: vler %v0, 0, 15
-0xe6 0x00 0x00 0x00 0xf0 0x07
-
-# CHECK: vler %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x07
-
-# CHECK: vler %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x07
-
-# CHECK: vler %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x07
-
-# CHECK: vler %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x07
-
-# CHECK: vler %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x07
-
-# CHECK: vler %v18, 1383(%r3,%r4), 11
-0xe6 0x23 0x45 0x67 0xb8 0x07
-
-# CHECK: vlerf %v0, 0
-0xe6 0x00 0x00 0x00 0x20 0x07
-
-# CHECK: vlerf %v0, 4095
-0xe6 0x00 0x0f 0xff 0x20 0x07
-
-# CHECK: vlerf %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x20 0x07
-
-# CHECK: vlerf %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x20 0x07
-
-# CHECK: vlerf %v15, 0
-0xe6 0xf0 0x00 0x00 0x20 0x07
-
-# CHECK: vlerf %v31, 0
-0xe6 0xf0 0x00 0x00 0x28 0x07
-
-# CHECK: vlerf %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x28 0x07
-
-# CHECK: vlerg %v0, 0
-0xe6 0x00 0x00 0x00 0x30 0x07
-
-# CHECK: vlerg %v0, 4095
-0xe6 0x00 0x0f 0xff 0x30 0x07
-
-# CHECK: vlerg %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x30 0x07
-
-# CHECK: vlerg %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x30 0x07
-
-# CHECK: vlerg %v15, 0
-0xe6 0xf0 0x00 0x00 0x30 0x07
-
-# CHECK: vlerg %v31, 0
-0xe6 0xf0 0x00 0x00 0x38 0x07
-
-# CHECK: vlerg %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x38 0x07
-
-# CHECK: vlerh %v0, 0
-0xe6 0x00 0x00 0x00 0x10 0x07
-
-# CHECK: vlerh %v0, 4095
-0xe6 0x00 0x0f 0xff 0x10 0x07
-
-# CHECK: vlerh %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x10 0x07
-
-# CHECK: vlerh %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x10 0x07
-
-# CHECK: vlerh %v15, 0
-0xe6 0xf0 0x00 0x00 0x10 0x07
-
-# CHECK: vlerh %v31, 0
-0xe6 0xf0 0x00 0x00 0x18 0x07
-
-# CHECK: vlerh %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x18 0x07
-
-# CHECK: vllebrz %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x04
-
-# CHECK: vllebrz %v0, 0, 15
-0xe6 0x00 0x00 0x00 0xf0 0x04
-
-# CHECK: vllebrz %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x04
-
-# CHECK: vllebrz %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x04
-
-# CHECK: vllebrz %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x04
-
-# CHECK: vllebrz %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x04
-
-# CHECK: vllebrz %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x04
-
-# CHECK: vllebrz %v18, 1383(%r3,%r4), 11
-0xe6 0x23 0x45 0x67 0xb8 0x04
-
-# CHECK: vllebrze %v0, 0
-0xe6 0x00 0x00 0x00 0x60 0x04
-
-# CHECK: vllebrze %v0, 4095
-0xe6 0x00 0x0f 0xff 0x60 0x04
-
-# CHECK: vllebrze %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x60 0x04
-
-# CHECK: vllebrze %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x60 0x04
-
-# CHECK: vllebrze %v15, 0
-0xe6 0xf0 0x00 0x00 0x60 0x04
-
-# CHECK: vllebrze %v31, 0
-0xe6 0xf0 0x00 0x00 0x68 0x04
-
-# CHECK: vllebrze %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x68 0x04
-
-# CHECK: vllebrzf %v0, 0
-0xe6 0x00 0x00 0x00 0x20 0x04
-
-# CHECK: vllebrzf %v0, 4095
-0xe6 0x00 0x0f 0xff 0x20 0x04
-
-# CHECK: vllebrzf %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x20 0x04
-
-# CHECK: vllebrzf %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x20 0x04
-
-# CHECK: vllebrzf %v15, 0
-0xe6 0xf0 0x00 0x00 0x20 0x04
-
-# CHECK: vllebrzf %v31, 0
-0xe6 0xf0 0x00 0x00 0x28 0x04
-
-# CHECK: vllebrzf %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x28 0x04
-
-# CHECK: vllebrzg %v0, 0
-0xe6 0x00 0x00 0x00 0x30 0x04
-
-# CHECK: vllebrzg %v0, 4095
-0xe6 0x00 0x0f 0xff 0x30 0x04
-
-# CHECK: vllebrzg %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x30 0x04
-
-# CHECK: vllebrzg %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x30 0x04
-
-# CHECK: vllebrzg %v15, 0
-0xe6 0xf0 0x00 0x00 0x30 0x04
-
-# CHECK: vllebrzg %v31, 0
-0xe6 0xf0 0x00 0x00 0x38 0x04
-
-# CHECK: vllebrzg %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x38 0x04
-
-# CHECK: vllebrzh %v0, 0
-0xe6 0x00 0x00 0x00 0x10 0x04
-
-# CHECK: vllebrzh %v0, 4095
-0xe6 0x00 0x0f 0xff 0x10 0x04
-
-# CHECK: vllebrzh %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x10 0x04
-
-# CHECK: vllebrzh %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x10 0x04
-
-# CHECK: vllebrzh %v15, 0
-0xe6 0xf0 0x00 0x00 0x10 0x04
-
-# CHECK: vllebrzh %v31, 0
-0xe6 0xf0 0x00 0x00 0x18 0x04
-
-# CHECK: vllebrzh %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x18 0x04
-
-# CHECK: vsld %v0, %v0, %v0, 0
-0xe7 0x00 0x00 0x00 0x00 0x86
-
-# CHECK: vsld %v0, %v0, %v0, 255
-0xe7 0x00 0x00 0xff 0x00 0x86
-
-# CHECK: vsld %v0, %v0, %v31, 0
-0xe7 0x00 0xf0 0x00 0x02 0x86
-
-# CHECK: vsld %v0, %v31, %v0, 0
-0xe7 0x0f 0x00 0x00 0x04 0x86
-
-# CHECK: vsld %v31, %v0, %v0, 0
-0xe7 0xf0 0x00 0x00 0x08 0x86
-
-# CHECK: vsld %v13, %v17, %v21, 121
-0xe7 0xd1 0x50 0x79 0x06 0x86
-
-# CHECK: vsrd %v0, %v0, %v0, 0
-0xe7 0x00 0x00 0x00 0x00 0x87
-
-# CHECK: vsrd %v0, %v0, %v0, 255
-0xe7 0x00 0x00 0xff 0x00 0x87
-
-# CHECK: vsrd %v0, %v0, %v31, 0
-0xe7 0x00 0xf0 0x00 0x02 0x87
-
-# CHECK: vsrd %v0, %v31, %v0, 0
-0xe7 0x0f 0x00 0x00 0x04 0x87
-
-# CHECK: vsrd %v31, %v0, %v0, 0
-0xe7 0xf0 0x00 0x00 0x08 0x87
-
-# CHECK: vsrd %v13, %v17, %v21, 121
-0xe7 0xd1 0x50 0x79 0x06 0x87
-
-# CHECK: vstbr %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x0e
-
-# CHECK: vstbr %v0, 0, 15
-0xe6 0x00 0x00 0x00 0xf0 0x0e
-
-# CHECK: vstbr %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x0e
-
-# CHECK: vstbr %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x0e
-
-# CHECK: vstbr %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x0e
-
-# CHECK: vstbr %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x0e
-
-# CHECK: vstbr %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x0e
-
-# CHECK: vstbr %v18, 1383(%r3,%r4), 11
-0xe6 0x23 0x45 0x67 0xb8 0x0e
-
-# CHECK: vstbrf %v0, 0
-0xe6 0x00 0x00 0x00 0x20 0x0e
-
-# CHECK: vstbrf %v0, 4095
-0xe6 0x00 0x0f 0xff 0x20 0x0e
-
-# CHECK: vstbrf %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x20 0x0e
-
-# CHECK: vstbrf %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x20 0x0e
-
-# CHECK: vstbrf %v15, 0
-0xe6 0xf0 0x00 0x00 0x20 0x0e
-
-# CHECK: vstbrf %v31, 0
-0xe6 0xf0 0x00 0x00 0x28 0x0e
-
-# CHECK: vstbrf %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x28 0x0e
-
-# CHECK: vstbrg %v0, 0
-0xe6 0x00 0x00 0x00 0x30 0x0e
-
-# CHECK: vstbrg %v0, 4095
-0xe6 0x00 0x0f 0xff 0x30 0x0e
-
-# CHECK: vstbrg %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x30 0x0e
-
-# CHECK: vstbrg %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x30 0x0e
-
-# CHECK: vstbrg %v15, 0
-0xe6 0xf0 0x00 0x00 0x30 0x0e
-
-# CHECK: vstbrg %v31, 0
-0xe6 0xf0 0x00 0x00 0x38 0x0e
-
-# CHECK: vstbrg %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x38 0x0e
-
-# CHECK: vstbrh %v0, 0
-0xe6 0x00 0x00 0x00 0x10 0x0e
-
-# CHECK: vstbrh %v0, 4095
-0xe6 0x00 0x0f 0xff 0x10 0x0e
-
-# CHECK: vstbrh %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x10 0x0e
-
-# CHECK: vstbrh %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x10 0x0e
-
-# CHECK: vstbrh %v15, 0
-0xe6 0xf0 0x00 0x00 0x10 0x0e
-
-# CHECK: vstbrh %v31, 0
-0xe6 0xf0 0x00 0x00 0x18 0x0e
-
-# CHECK: vstbrh %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x18 0x0e
-
-# CHECK: vstbrq %v0, 0
-0xe6 0x00 0x00 0x00 0x40 0x0e
-
-# CHECK: vstbrq %v0, 4095
-0xe6 0x00 0x0f 0xff 0x40 0x0e
-
-# CHECK: vstbrq %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x40 0x0e
-
-# CHECK: vstbrq %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x40 0x0e
-
-# CHECK: vstbrq %v15, 0
-0xe6 0xf0 0x00 0x00 0x40 0x0e
-
-# CHECK: vstbrq %v31, 0
-0xe6 0xf0 0x00 0x00 0x48 0x0e
-
-# CHECK: vstbrq %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x48 0x0e
-
-# CHECK: vstebrf %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x0b
-
-# CHECK: vstebrf %v0, 0, 3
-0xe6 0x00 0x00 0x00 0x30 0x0b
-
-# CHECK: vstebrf %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x0b
-
-# CHECK: vstebrf %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x0b
-
-# CHECK: vstebrf %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x0b
-
-# CHECK: vstebrf %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x0b
-
-# CHECK: vstebrf %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x0b
-
-# CHECK: vstebrf %v18, 1383(%r3,%r4), 2
-0xe6 0x23 0x45 0x67 0x28 0x0b
-
-# CHECK: vstebrg %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x0a
-
-# CHECK: vstebrg %v0, 0, 1
-0xe6 0x00 0x00 0x00 0x10 0x0a
-
-# CHECK: vstebrg %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x0a
-
-# CHECK: vstebrg %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x0a
-
-# CHECK: vstebrg %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x0a
-
-# CHECK: vstebrg %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x0a
-
-# CHECK: vstebrg %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x0a
-
-# CHECK: vstebrg %v18, 1383(%r3,%r4), 1
-0xe6 0x23 0x45 0x67 0x18 0x0a
-
-# CHECK: vstebrh %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x09
-
-# CHECK: vstebrh %v0, 0, 7
-0xe6 0x00 0x00 0x00 0x70 0x09
-
-# CHECK: vstebrh %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x09
-
-# CHECK: vstebrh %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x09
-
-# CHECK: vstebrh %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x09
-
-# CHECK: vstebrh %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x09
-
-# CHECK: vstebrh %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x09
-
-# CHECK: vstebrh %v18, 1383(%r3,%r4), 4
-0xe6 0x23 0x45 0x67 0x48 0x09
-
-# CHECK: vster %v0, 0, 0
-0xe6 0x00 0x00 0x00 0x00 0x0f
-
-# CHECK: vster %v0, 0, 15
-0xe6 0x00 0x00 0x00 0xf0 0x0f
-
-# CHECK: vster %v0, 4095, 0
-0xe6 0x00 0x0f 0xff 0x00 0x0f
-
-# CHECK: vster %v0, 0(%r15), 0
-0xe6 0x00 0xf0 0x00 0x00 0x0f
-
-# CHECK: vster %v0, 0(%r15,%r1), 0
-0xe6 0x0f 0x10 0x00 0x00 0x0f
-
-# CHECK: vster %v15, 0, 0
-0xe6 0xf0 0x00 0x00 0x00 0x0f
-
-# CHECK: vster %v31, 0, 0
-0xe6 0xf0 0x00 0x00 0x08 0x0f
-
-# CHECK: vster %v18, 1383(%r3,%r4), 11
-0xe6 0x23 0x45 0x67 0xb8 0x0f
-
-# CHECK: vsterf %v0, 0
-0xe6 0x00 0x00 0x00 0x20 0x0f
-
-# CHECK: vsterf %v0, 4095
-0xe6 0x00 0x0f 0xff 0x20 0x0f
-
-# CHECK: vsterf %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x20 0x0f
-
-# CHECK: vsterf %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x20 0x0f
-
-# CHECK: vsterf %v15, 0
-0xe6 0xf0 0x00 0x00 0x20 0x0f
-
-# CHECK: vsterf %v31, 0
-0xe6 0xf0 0x00 0x00 0x28 0x0f
-
-# CHECK: vsterf %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x28 0x0f
-
-# CHECK: vsterg %v0, 0
-0xe6 0x00 0x00 0x00 0x30 0x0f
-
-# CHECK: vsterg %v0, 4095
-0xe6 0x00 0x0f 0xff 0x30 0x0f
-
-# CHECK: vsterg %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x30 0x0f
-
-# CHECK: vsterg %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x30 0x0f
-
-# CHECK: vsterg %v15, 0
-0xe6 0xf0 0x00 0x00 0x30 0x0f
-
-# CHECK: vsterg %v31, 0
-0xe6 0xf0 0x00 0x00 0x38 0x0f
-
-# CHECK: vsterg %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x38 0x0f
-
-# CHECK: vsterh %v0, 0
-0xe6 0x00 0x00 0x00 0x10 0x0f
-
-# CHECK: vsterh %v0, 4095
-0xe6 0x00 0x0f 0xff 0x10 0x0f
-
-# CHECK: vsterh %v0, 0(%r15)
-0xe6 0x00 0xf0 0x00 0x10 0x0f
-
-# CHECK: vsterh %v0, 0(%r15,%r1)
-0xe6 0x0f 0x10 0x00 0x10 0x0f
-
-# CHECK: vsterh %v15, 0
-0xe6 0xf0 0x00 0x00 0x10 0x0f
-
-# CHECK: vsterh %v31, 0
-0xe6 0xf0 0x00 0x00 0x18 0x0f
-
-# CHECK: vsterh %v18, 1383(%r3,%r4)
-0xe6 0x23 0x45 0x67 0x18 0x0f
-
-# CHECK: vstrs %v0, %v0, %v0, %v0, 11, 0
-0xe7 0x00 0x0b 0x00 0x00 0x8b
-
-# CHECK: vstrs %v0, %v0, %v0, %v0, 11, 12
-0xe7 0x00 0x0b 0xc0 0x00 0x8b
-
-# CHECK: vstrs %v18, %v3, %v20, %v5, 11, 0
-0xe7 0x23 0x4b 0x00 0x5a 0x8b
-
-# CHECK: vstrs %v31, %v31, %v31, %v31, 11, 4
-0xe7 0xff 0xfb 0x40 0xff 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v0, %v0, 0
-0xe7 0x00 0x00 0x00 0x00 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v0, %v0, 0
-0xe7 0x00 0x00 0x00 0x00 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v0, %v0, 12
-0xe7 0x00 0x00 0xc0 0x00 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v0, %v15, 0
-0xe7 0x00 0x00 0x00 0xf0 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v0, %v31, 0
-0xe7 0x00 0x00 0x00 0xf1 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v15, %v0, 0
-0xe7 0x00 0xf0 0x00 0x00 0x8b
-
-# CHECK: vstrsb %v0, %v0, %v31, %v0, 0
-0xe7 0x00 0xf0 0x00 0x02 0x8b
-
-# CHECK: vstrsb %v0, %v15, %v0, %v0, 0
-0xe7 0x0f 0x00 0x00 0x00 0x8b
-
-# CHECK: vstrsb %v0, %v31, %v0, %v0, 0
-0xe7 0x0f 0x00 0x00 0x04 0x8b
-
-# CHECK: vstrsb %v15, %v0, %v0, %v0, 0
-0xe7 0xf0 0x00 0x00 0x00 0x8b
-
-# CHECK: vstrsb %v31, %v0, %v0, %v0, 0
-0xe7 0xf0 0x00 0x00 0x08 0x8b
-
-# CHECK: vstrsb %v18, %v3, %v20, %v5, 4
-0xe7 0x23 0x40 0x40 0x5a 0x8b
-
-# CHECK: vstrsb %v18, %v3, %v20, %v5, 12
-0xe7 0x23 0x40 0xc0 0x5a 0x8b
-
-# CHECK: vstrszb %v18, %v3, %v20, %v5
-0xe7 0x23 0x40 0x20 0x5a 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v0, %v0, 0
-0xe7 0x00 0x02 0x00 0x00 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v0, %v0, 0
-0xe7 0x00 0x02 0x00 0x00 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v0, %v0, 12
-0xe7 0x00 0x02 0xc0 0x00 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v0, %v15, 0
-0xe7 0x00 0x02 0x00 0xf0 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v0, %v31, 0
-0xe7 0x00 0x02 0x00 0xf1 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v15, %v0, 0
-0xe7 0x00 0xf2 0x00 0x00 0x8b
-
-# CHECK: vstrsf %v0, %v0, %v31, %v0, 0
-0xe7 0x00 0xf2 0x00 0x02 0x8b
-
-# CHECK: vstrsf %v0, %v15, %v0, %v0, 0
-0xe7 0x0f 0x02 0x00 0x00 0x8b
-
-# CHECK: vstrsf %v0, %v31, %v0, %v0, 0
-0xe7 0x0f 0x02 0x00 0x04 0x8b
-
-# CHECK: vstrsf %v15, %v0, %v0, %v0, 0
-0xe7 0xf0 0x02 0x00 0x00 0x8b
-
-# CHECK: vstrsf %v31, %v0, %v0, %v0, 0
-0xe7 0xf0 0x02 0x00 0x08 0x8b
-
-# CHECK: vstrsf %v18, %v3, %v20, %v5, 4
-0xe7 0x23 0x42 0x40 0x5a 0x8b
-
-# CHECK: vstrsf %v18, %v3, %v20, %v5, 12
-0xe7 0x23 0x42 0xc0 0x5a 0x8b
-
-# CHECK: vstrszf %v18, %v3, %v20, %v5
-0xe7 0x23 0x42 0x20 0x5a 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v0, %v0, 0
-0xe7 0x00 0x01 0x00 0x00 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v0, %v0, 0
-0xe7 0x00 0x01 0x00 0x00 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v0, %v0, 12
-0xe7 0x00 0x01 0xc0 0x00 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v0, %v15, 0
-0xe7 0x00 0x01 0x00 0xf0 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v0, %v31, 0
-0xe7 0x00 0x01 0x00 0xf1 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v15, %v0, 0
-0xe7 0x00 0xf1 0x00 0x00 0x8b
-
-# CHECK: vstrsh %v0, %v0, %v31, %v0, 0
-0xe7 0x00 0xf1 0x00 0x02 0x8b
-
-# CHECK: vstrsh %v0, %v15, %v0, %v0, 0
-0xe7 0x0f 0x01 0x00 0x00 0x8b
-
-# CHECK: vstrsh %v0, %v31, %v0, %v0, 0
-0xe7 0x0f 0x01 0x00 0x04 0x8b
-
-# CHECK: vstrsh %v15, %v0, %v0, %v0, 0
-0xe7 0xf0 0x01 0x00 0x00 0x8b
-
-# CHECK: vstrsh %v31, %v0, %v0, %v0, 0
-0xe7 0xf0 0x01 0x00 0x08 0x8b
-
-# CHECK: vstrsh %v18, %v3, %v20, %v5, 4
-0xe7 0x23 0x41 0x40 0x5a 0x8b
-
-# CHECK: vstrsh %v18, %v3, %v20, %v5, 12
-0xe7 0x23 0x41 0xc0 0x5a 0x8b
-
-# CHECK: vstrszh %v18, %v3, %v20, %v5
-0xe7 0x23 0x41 0x20 0x5a 0x8b
-
-# CHECK: wcefb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc3
-
-# CHECK: wcefb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc3
-
-# CHECK: wcefb %f0, %f0, 0, 15
-0xe7 0x00 0x00 0xf8 0x20 0xc3
-
-# CHECK: wcefb %f0, %f0, 4, 0
-0xe7 0x00 0x00 0x0c 0x20 0xc3
-
-# CHECK: wcefb %f0, %v31, 0, 0
-0xe7 0x0f 0x00 0x08 0x24 0xc3
-
-# CHECK: wcefb %v31, %f0, 0, 0
-0xe7 0xf0 0x00 0x08 0x28 0xc3
-
-# CHECK: wcefb %f14, %v17, 4, 10
-0xe7 0xe1 0x00 0xac 0x24 0xc3
-
-# CHECK: wcelfb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc1
-
-# CHECK: wcelfb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc1
-
-# CHECK: wcelfb %f0, %f0, 0, 15
-0xe7 0x00 0x00 0xf8 0x20 0xc1
-
-# CHECK: wcelfb %f0, %f0, 4, 0
-0xe7 0x00 0x00 0x0c 0x20 0xc1
-
-# CHECK: wcelfb %f0, %v31, 0, 0
-0xe7 0x0f 0x00 0x08 0x24 0xc1
-
-# CHECK: wcelfb %v31, %f0, 0, 0
-0xe7 0xf0 0x00 0x08 0x28 0xc1
-
-# CHECK: wcelfb %f14, %v17, 4, 10
-0xe7 0xe1 0x00 0xac 0x24 0xc1
-
-# CHECK: wcfeb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc2
-
-# CHECK: wcfeb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc2
-
-# CHECK: wcfeb %f0, %f0, 0, 15
-0xe7 0x00 0x00 0xf8 0x20 0xc2
-
-# CHECK: wcfeb %f0, %f0, 4, 0
-0xe7 0x00 0x00 0x0c 0x20 0xc2
-
-# CHECK: wcfeb %f0, %v31, 0, 0
-0xe7 0x0f 0x00 0x08 0x24 0xc2
-
-# CHECK: wcfeb %v31, %f0, 0, 0
-0xe7 0xf0 0x00 0x08 0x28 0xc2
-
-# CHECK: wcfeb %f14, %v17, 4, 10
-0xe7 0xe1 0x00 0xac 0x24 0xc2
-
-# CHECK: wclfeb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc0
-
-# CHECK: wclfeb %f0, %f0, 0, 0
-0xe7 0x00 0x00 0x08 0x20 0xc0
-
-# CHECK: wclfeb %f0, %f0, 0, 15
-0xe7 0x00 0x00 0xf8 0x20 0xc0
-
-# CHECK: wclfeb %f0, %f0, 4, 0
-0xe7 0x00 0x00 0x0c 0x20 0xc0
-
-# CHECK: wclfeb %f0, %v31, 0, 0
-0xe7 0x0f 0x00 0x08 0x24 0xc0
-
-# CHECK: wclfeb %v31, %f0, 0, 0
-0xe7 0xf0 0x00 0x08 0x28 0xc0
-
-# CHECK: wclfeb %f14, %v17, 4, 10
-0xe7 0xe1 0x00 0xac 0x24 0xc0

Copied: llvm/trunk/test/MC/Disassembler/SystemZ/insns-z15.txt (from r372434, llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns-z15.txt?p2=llvm/trunk/test/MC/Disassembler/SystemZ/insns-z15.txt&p1=llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt&r1=372434&r2=372435&rev=372435&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns-arch13.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns-z15.txt Fri Sep 20 16:04:45 2019
@@ -1,5 +1,5 @@
-# Test arch13 instructions that don't have PC-relative operands.
-# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=arch13 \
+# Test z15 instructions that don't have PC-relative operands.
+# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z15 \
 # RUN:   | FileCheck %s
 
 # CHECK: dfltcc %r2, %r2, %r2

Removed: llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s?rev=372434&view=auto
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s (removed)
@@ -1,881 +0,0 @@
-# For arch13 only.
-# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch13 < %s 2> %t
-# RUN: FileCheck < %t %s
-
-#CHECK: error: invalid register pair
-#CHECK: dfltcc	%r1, %r2, %r4
-#CHECK: error: invalid register pair
-#CHECK: dfltcc	%r2, %r1, %r4
-
-	dfltcc	%r1, %r2, %r4
-	dfltcc	%r2, %r1, %r4
-
-#CHECK: error: invalid register pair
-#CHECK: kdsa	%r0, %r1
-
-	kdsa	%r0, %r1
-
-#CHECK: error: invalid operand
-#CHECK: ldrv	%f0, -1
-#CHECK: error: invalid operand
-#CHECK: ldrv	%f0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: ldrv	%f0, 0(%v1,%r2)
-
-	ldrv	%f0, -1
-	ldrv	%f0, 4096
-	ldrv	%f0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: lerv	%f0, -1
-#CHECK: error: invalid operand
-#CHECK: lerv	%f0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: lerv	%f0, 0(%v1,%r2)
-
-	lerv	%f0, -1
-	lerv	%f0, 4096
-	lerv	%f0, 0(%v1,%r2)
-
-#CHECK: error: invalid use of indexed addressing
-#CHECK: mvcrl	160(%r1,%r15),160(%r15)
-#CHECK: error: invalid operand
-#CHECK: mvcrl	-1(%r1),160(%r15)
-#CHECK: error: invalid operand
-#CHECK: mvcrl	4096(%r1),160(%r15)
-#CHECK: error: invalid operand
-#CHECK: mvcrl	0(%r1),-1(%r15)
-#CHECK: error: invalid operand
-#CHECK: mvcrl	0(%r1),4096(%r15)
-
-        mvcrl	160(%r1,%r15),160(%r15)
-        mvcrl	-1(%r1),160(%r15)
-        mvcrl	4096(%r1),160(%r15)
-        mvcrl	0(%r1),-1(%r15)
-        mvcrl	0(%r1),4096(%r15)
-
-#CHECK: error: invalid operand
-#CHECK: popcnt	%r2, %r4, -1
-#CHECK: error: invalid operand
-#CHECK: popcnt	%r2, %r4, 16
-
-	popcnt	%r2, %r4, -1
-	popcnt	%r2, %r4, 16
-
-#CHECK: error: invalid operand
-#CHECK: selgr	%r0, %r0, %r0, -1
-#CHECK: error: invalid operand
-#CHECK: selgr	%r0, %r0, %r0, 16
-
-	selgr	%r0, %r0, %r0, -1
-	selgr	%r0, %r0, %r0, 16
-
-#CHECK: error: invalid operand
-#CHECK: selfhr	%r0, %r0, %r0, -1
-#CHECK: error: invalid operand
-#CHECK: selfhr	%r0, %r0, %r0, 16
-
-	selfhr	%r0, %r0, %r0, -1
-	selfhr	%r0, %r0, %r0, 16
-
-#CHECK: error: invalid operand
-#CHECK: selr	%r0, %r0, %r0, -1
-#CHECK: error: invalid operand
-#CHECK: selr	%r0, %r0, %r0, 16
-
-	selr	%r0, %r0, %r0, -1
-	selr	%r0, %r0, %r0, 16
-
-#CHECK: error: invalid register pair
-#CHECK: sortl	%r1, %r2
-#CHECK: error: invalid register pair
-#CHECK: sortl	%r2, %r1
-
-	sortl	%r1, %r2
-	sortl	%r2, %r1
-
-#CHECK: error: invalid operand
-#CHECK: stdrv	%f0, -1
-#CHECK: error: invalid operand
-#CHECK: stdrv	%f0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: stdrv	%f0, 0(%v1,%r2)
-
-	stdrv	%f0, -1
-	stdrv	%f0, 4096
-	stdrv	%f0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: sterv	%f0, -1
-#CHECK: error: invalid operand
-#CHECK: sterv	%f0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: sterv	%f0, 0(%v1,%r2)
-
-	sterv	%f0, -1
-	sterv	%f0, 4096
-	sterv	%f0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vcefb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcefb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vcefb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vcefb	%v0, %v0, 16, 0
-
-	vcefb	%v0, %v0, 0, -1
-	vcefb	%v0, %v0, 0, 16
-	vcefb	%v0, %v0, -1, 0
-	vcefb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: vcelfb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcelfb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vcelfb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vcelfb	%v0, %v0, 16, 0
-
-	vcelfb	%v0, %v0, 0, -1
-	vcelfb	%v0, %v0, 0, 16
-	vcelfb	%v0, %v0, -1, 0
-	vcelfb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: vcfeb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcfeb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vcfeb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vcfeb	%v0, %v0, 16, 0
-
-	vcfeb	%v0, %v0, 0, -1
-	vcfeb	%v0, %v0, 0, 16
-	vcfeb	%v0, %v0, -1, 0
-	vcfeb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: vcfpl	%v0, %v0, 0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcfpl	%v0, %v0, 0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vcfpl	%v0, %v0, 0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vcfpl	%v0, %v0, 0, 16, 0
-#CHECK: error: invalid operand
-#CHECK: vcfpl	%v0, %v0, -1, 0, 0
-#CHECK: error: invalid operand
-#CHECK: vcfpl	%v0, %v0, 16, 0, 0
-
-	vcfpl	%v0, %v0, 0, 0, -1
-	vcfpl	%v0, %v0, 0, 0, 16
-	vcfpl	%v0, %v0, 0, -1, 0
-	vcfpl	%v0, %v0, 0, 16, 0
-	vcfpl	%v0, %v0, -1, 0, 0
-	vcfpl	%v0, %v0, 16, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vcfps	%v0, %v0, 0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcfps	%v0, %v0, 0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vcfps	%v0, %v0, 0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vcfps	%v0, %v0, 0, 16, 0
-#CHECK: error: invalid operand
-#CHECK: vcfps	%v0, %v0, -1, 0, 0
-#CHECK: error: invalid operand
-#CHECK: vcfps	%v0, %v0, 16, 0, 0
-
-	vcfps	%v0, %v0, 0, 0, -1
-	vcfps	%v0, %v0, 0, 0, 16
-	vcfps	%v0, %v0, 0, -1, 0
-	vcfps	%v0, %v0, 0, 16, 0
-	vcfps	%v0, %v0, -1, 0, 0
-	vcfps	%v0, %v0, 16, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vclfeb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vclfeb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vclfeb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vclfeb	%v0, %v0, 16, 0
-
-	vclfeb	%v0, %v0, 0, -1
-	vclfeb	%v0, %v0, 0, 16
-	vclfeb	%v0, %v0, -1, 0
-	vclfeb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: vclfp	%v0, %v0, 0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vclfp	%v0, %v0, 0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vclfp	%v0, %v0, 0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vclfp	%v0, %v0, 0, 16, 0
-#CHECK: error: invalid operand
-#CHECK: vclfp	%v0, %v0, -1, 0, 0
-#CHECK: error: invalid operand
-#CHECK: vclfp	%v0, %v0, 16, 0, 0
-
-	vclfp	%v0, %v0, 0, 0, -1
-	vclfp	%v0, %v0, 0, 0, 16
-	vclfp	%v0, %v0, 0, -1, 0
-	vclfp	%v0, %v0, 0, 16, 0
-	vclfp	%v0, %v0, -1, 0, 0
-	vclfp	%v0, %v0, 16, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vcsfp	%v0, %v0, 0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcsfp	%v0, %v0, 0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vcsfp	%v0, %v0, 0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vcsfp	%v0, %v0, 0, 16, 0
-#CHECK: error: invalid operand
-#CHECK: vcsfp	%v0, %v0, -1, 0, 0
-#CHECK: error: invalid operand
-#CHECK: vcsfp	%v0, %v0, 16, 0, 0
-
-	vcsfp	%v0, %v0, 0, 0, -1
-	vcsfp	%v0, %v0, 0, 0, 16
-	vcsfp	%v0, %v0, 0, -1, 0
-	vcsfp	%v0, %v0, 0, 16, 0
-	vcsfp	%v0, %v0, -1, 0, 0
-	vcsfp	%v0, %v0, 16, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vcvb	%r0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcvb	%r0, %v0, 0, 16
-
-	vcvb	%r0, %v0, 0, -1
-	vcvb	%r0, %v0, 0, 16
-
-#CHECK: error: invalid operand
-#CHECK: vcvbg	%r0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vcvbg	%r0, %v0, 0, 16
-
-	vcvbg	%r0, %v0, 0, -1
-	vcvbg	%r0, %v0, 0, 16
-
-#CHECK: error: invalid operand
-#CHECK: vlbr	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbr	%v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vlbr	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vlbr	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbr	%v0, 0(%v1,%r2), 0
-
-	vlbr	%v0, 0, -1
-	vlbr	%v0, 0, 16
-	vlbr	%v0, -1, 0
-	vlbr	%v0, 4096, 0
-	vlbr	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vlbrf	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrf	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrf	%v0, 0(%v1,%r2)
-
-	vlbrf	%v0, -1
-	vlbrf	%v0, 4096
-	vlbrf	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlbrg	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrg	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrg	%v0, 0(%v1,%r2)
-
-	vlbrg	%v0, -1
-	vlbrg	%v0, 4096
-	vlbrg	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlbrh	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrh	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrh	%v0, 0(%v1,%r2)
-
-	vlbrh	%v0, -1
-	vlbrh	%v0, 4096
-	vlbrh	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlbrq	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrq	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrq	%v0, 0(%v1,%r2)
-
-	vlbrq	%v0, -1
-	vlbrq	%v0, 4096
-	vlbrq	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlbrrep	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrrep	%v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vlbrrep	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vlbrrep	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrrep	%v0, 0(%v1,%r2), 0
-
-	vlbrrep	%v0, 0, -1
-	vlbrrep	%v0, 0, 16
-	vlbrrep	%v0, -1, 0
-	vlbrrep	%v0, 4096, 0
-	vlbrrep	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vlbrrepf %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrrepf %v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrrepf %v0, 0(%v1,%r2)
-
-	vlbrrepf %v0, -1
-	vlbrrepf %v0, 4096
-	vlbrrepf %v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlbrrepg %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrrepg %v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrrepg %v0, 0(%v1,%r2)
-
-	vlbrrepg %v0, -1
-	vlbrrepg %v0, 4096
-	vlbrrepg %v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlbrreph %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlbrreph %v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlbrreph %v0, 0(%v1,%r2)
-
-	vlbrreph %v0, -1
-	vlbrreph %v0, 4096
-	vlbrreph %v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlebrf	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vlebrf	%v0, 0, 4
-#CHECK: error: invalid operand
-#CHECK: vlebrf	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vlebrf	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlebrf	%v0, 0(%v1,%r2), 0
-
-	vlebrf	%v0, 0, -1
-	vlebrf	%v0, 0, 4
-	vlebrf	%v0, -1, 0
-	vlebrf	%v0, 4096, 0
-	vlebrf	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vlebrg	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vlebrg	%v0, 0, 2
-#CHECK: error: invalid operand
-#CHECK: vlebrg	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vlebrg	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlebrg	%v0, 0(%v1,%r2), 0
-
-	vlebrg	%v0, 0, -1
-	vlebrg	%v0, 0, 2
-	vlebrg	%v0, -1, 0
-	vlebrg	%v0, 4096, 0
-	vlebrg	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vlebrh	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vlebrh	%v0, 0, 8
-#CHECK: error: invalid operand
-#CHECK: vlebrh	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vlebrh	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlebrh	%v0, 0(%v1,%r2), 0
-
-	vlebrh	%v0, 0, -1
-	vlebrh	%v0, 0, 8
-	vlebrh	%v0, -1, 0
-	vlebrh	%v0, 4096, 0
-	vlebrh	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vler	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vler	%v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vler	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vler	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vler	%v0, 0(%v1,%r2), 0
-
-	vler	%v0, 0, -1
-	vler	%v0, 0, 16
-	vler	%v0, -1, 0
-	vler	%v0, 4096, 0
-	vler	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vlerf	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlerf	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlerf	%v0, 0(%v1,%r2)
-
-	vlerf	%v0, -1
-	vlerf	%v0, 4096
-	vlerf	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlerg	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlerg	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlerg	%v0, 0(%v1,%r2)
-
-	vlerg	%v0, -1
-	vlerg	%v0, 4096
-	vlerg	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vlerh	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vlerh	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vlerh	%v0, 0(%v1,%r2)
-
-	vlerh	%v0, -1
-	vlerh	%v0, 4096
-	vlerh	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vllebrz	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vllebrz	%v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vllebrz	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vllebrz	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vllebrz	%v0, 0(%v1,%r2), 0
-
-	vllebrz	%v0, 0, -1
-	vllebrz	%v0, 0, 16
-	vllebrz	%v0, -1, 0
-	vllebrz	%v0, 4096, 0
-	vllebrz	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vllebrze	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vllebrze	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vllebrze	%v0, 0(%v1,%r2)
-
-	vllebrze	%v0, -1
-	vllebrze	%v0, 4096
-	vllebrze	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vllebrzf	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vllebrzf	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vllebrzf	%v0, 0(%v1,%r2)
-
-	vllebrzf	%v0, -1
-	vllebrzf	%v0, 4096
-	vllebrzf	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vllebrzg	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vllebrzg	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vllebrzg	%v0, 0(%v1,%r2)
-
-	vllebrzg	%v0, -1
-	vllebrzg	%v0, 4096
-	vllebrzg	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vllebrzh	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vllebrzh	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vllebrzh	%v0, 0(%v1,%r2)
-
-	vllebrzh	%v0, -1
-	vllebrzh	%v0, 4096
-	vllebrzh	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vsld	%v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vsld	%v0, %v0, %v0, 256
-
-	vsld	%v0, %v0, %v0, -1
-	vsld	%v0, %v0, %v0, 256
-
-#CHECK: error: invalid operand
-#CHECK: vsrd	%v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vsrd	%v0, %v0, %v0, 256
-
-	vsrd	%v0, %v0, %v0, -1
-	vsrd	%v0, %v0, %v0, 256
-
-#CHECK: error: invalid operand
-#CHECK: vstbr	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vstbr	%v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vstbr	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vstbr	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstbr	%v0, 0(%v1,%r2), 0
-
-	vstbr	%v0, 0, -1
-	vstbr	%v0, 0, 16
-	vstbr	%v0, -1, 0
-	vstbr	%v0, 4096, 0
-	vstbr	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vstbrf	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstbrf	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstbrf	%v0, 0(%v1,%r2)
-
-	vstbrf	%v0, -1
-	vstbrf	%v0, 4096
-	vstbrf	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vstbrg	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstbrg	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstbrg	%v0, 0(%v1,%r2)
-
-	vstbrg	%v0, -1
-	vstbrg	%v0, 4096
-	vstbrg	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vstbrh	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstbrh	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstbrh	%v0, 0(%v1,%r2)
-
-	vstbrh	%v0, -1
-	vstbrh	%v0, 4096
-	vstbrh	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vstbrq	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstbrq	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstbrq	%v0, 0(%v1,%r2)
-
-	vstbrq	%v0, -1
-	vstbrq	%v0, 4096
-	vstbrq	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vstebrf	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vstebrf	%v0, 0, 4
-#CHECK: error: invalid operand
-#CHECK: vstebrf	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vstebrf	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstebrf	%v0, 0(%v1,%r2), 0
-
-	vstebrf	%v0, 0, -1
-	vstebrf	%v0, 0, 4
-	vstebrf	%v0, -1, 0
-	vstebrf	%v0, 4096, 0
-	vstebrf	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vstebrg	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vstebrg	%v0, 0, 2
-#CHECK: error: invalid operand
-#CHECK: vstebrg	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vstebrg	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstebrg	%v0, 0(%v1,%r2), 0
-
-	vstebrg	%v0, 0, -1
-	vstebrg	%v0, 0, 2
-	vstebrg	%v0, -1, 0
-	vstebrg	%v0, 4096, 0
-	vstebrg	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vstebrh	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vstebrh	%v0, 0, 8
-#CHECK: error: invalid operand
-#CHECK: vstebrh	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vstebrh	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vstebrh	%v0, 0(%v1,%r2), 0
-
-	vstebrh	%v0, 0, -1
-	vstebrh	%v0, 0, 8
-	vstebrh	%v0, -1, 0
-	vstebrh	%v0, 4096, 0
-	vstebrh	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vster	%v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vster	%v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vster	%v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vster	%v0, 4096, 0
-#CHECK: error: invalid use of vector addressing
-#CHECK: vster	%v0, 0(%v1,%r2), 0
-
-	vster	%v0, 0, -1
-	vster	%v0, 0, 16
-	vster	%v0, -1, 0
-	vster	%v0, 4096, 0
-	vster	%v0, 0(%v1,%r2), 0
-
-#CHECK: error: invalid operand
-#CHECK: vsterf	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vsterf	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vsterf	%v0, 0(%v1,%r2)
-
-	vsterf	%v0, -1
-	vsterf	%v0, 4096
-	vsterf	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vsterg	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vsterg	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vsterg	%v0, 0(%v1,%r2)
-
-	vsterg	%v0, -1
-	vsterg	%v0, 4096
-	vsterg	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vsterh	%v0, -1
-#CHECK: error: invalid operand
-#CHECK: vsterh	%v0, 4096
-#CHECK: error: invalid use of vector addressing
-#CHECK: vsterh	%v0, 0(%v1,%r2)
-
-	vsterh	%v0, -1
-	vsterh	%v0, 4096
-	vsterh	%v0, 0(%v1,%r2)
-
-#CHECK: error: invalid operand
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: vstrs    %v0, %v0, %v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 16, 0
-#CHECK: error: too few operands
-#CHECK: vstrs    %v0, %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 0, 0, 0
-
-	vstrs    %v0, %v0, %v0, %v0, 0, -1
-	vstrs    %v0, %v0, %v0, %v0, 0, 16
-	vstrs    %v0, %v0, %v0, %v0, -1, 0
-	vstrs    %v0, %v0, %v0, %v0, 16, 0
-	vstrs    %v0, %v0, %v0, %v0
-	vstrs    %v0, %v0, %v0, %v0, 0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vstrsb   %v0, %v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrsb   %v0, %v0, %v0, %v0, 16
-#CHECK: error: too few operands
-#CHECK: vstrsb   %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrsb   %v0, %v0, %v0, %v0, 0, 0
-
-	vstrsb   %v0, %v0, %v0, %v0, -1
-	vstrsb   %v0, %v0, %v0, %v0, 16
-	vstrsb   %v0, %v0, %v0
-	vstrsb   %v0, %v0, %v0, %v0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vstrsf   %v0, %v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrsf   %v0, %v0, %v0, %v0, 16
-#CHECK: error: too few operands
-#CHECK: vstrsf   %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrsf   %v0, %v0, %v0, %v0, 0, 0
-
-	vstrsf   %v0, %v0, %v0, %v0, -1
-	vstrsf   %v0, %v0, %v0, %v0, 16
-	vstrsf   %v0, %v0, %v0
-	vstrsf   %v0, %v0, %v0, %v0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vstrsh   %v0, %v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrsh   %v0, %v0, %v0, %v0, 16
-#CHECK: error: too few operands
-#CHECK: vstrsh   %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrsh   %v0, %v0, %v0, %v0, 0, 0
-
-	vstrsh   %v0, %v0, %v0, %v0, -1
-	vstrsh   %v0, %v0, %v0, %v0, 16
-	vstrsh   %v0, %v0, %v0
-	vstrsh   %v0, %v0, %v0, %v0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vstrszb  %v0, %v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrszb  %v0, %v0, %v0, %v0, 16
-#CHECK: error: too few operands
-#CHECK: vstrszb  %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrszb  %v0, %v0, %v0, %v0, 0, 0
-
-	vstrszb  %v0, %v0, %v0, %v0, -1
-	vstrszb  %v0, %v0, %v0, %v0, 16
-	vstrszb  %v0, %v0, %v0
-	vstrszb  %v0, %v0, %v0, %v0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vstrszf  %v0, %v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrszf  %v0, %v0, %v0, %v0, 16
-#CHECK: error: too few operands
-#CHECK: vstrszf  %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrszf  %v0, %v0, %v0, %v0, 0, 0
-
-	vstrszf  %v0, %v0, %v0, %v0, -1
-	vstrszf  %v0, %v0, %v0, %v0, 16
-	vstrszf  %v0, %v0, %v0
-	vstrszf  %v0, %v0, %v0, %v0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: vstrszh  %v0, %v0, %v0, %v0, -1
-#CHECK: error: invalid operand
-#CHECK: vstrszh  %v0, %v0, %v0, %v0, 16
-#CHECK: error: too few operands
-#CHECK: vstrszh  %v0, %v0, %v0
-#CHECK: error: invalid operand
-#CHECK: vstrszh  %v0, %v0, %v0, %v0, 0, 0
-
-	vstrszh  %v0, %v0, %v0, %v0, -1
-	vstrszh  %v0, %v0, %v0, %v0, 16
-	vstrszh  %v0, %v0, %v0
-	vstrszh  %v0, %v0, %v0, %v0, 0, 0
-
-#CHECK: error: invalid operand
-#CHECK: wcefb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: wcefb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: wcefb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: wcefb	%v0, %v0, 16, 0
-
-	wcefb	%v0, %v0, 0, -1
-	wcefb	%v0, %v0, 0, 16
-	wcefb	%v0, %v0, -1, 0
-	wcefb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: wcelfb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: wcelfb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: wcelfb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: wcelfb	%v0, %v0, 16, 0
-
-	wcelfb	%v0, %v0, 0, -1
-	wcelfb	%v0, %v0, 0, 16
-	wcelfb	%v0, %v0, -1, 0
-	wcelfb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: wcfeb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: wcfeb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: wcfeb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: wcfeb	%v0, %v0, 16, 0
-
-	wcfeb	%v0, %v0, 0, -1
-	wcfeb	%v0, %v0, 0, 16
-	wcfeb	%v0, %v0, -1, 0
-	wcfeb	%v0, %v0, 16, 0
-
-#CHECK: error: invalid operand
-#CHECK: wclfeb	%v0, %v0, 0, -1
-#CHECK: error: invalid operand
-#CHECK: wclfeb	%v0, %v0, 0, 16
-#CHECK: error: invalid operand
-#CHECK: wclfeb	%v0, %v0, -1, 0
-#CHECK: error: invalid operand
-#CHECK: wclfeb	%v0, %v0, 16, 0
-
-	wclfeb	%v0, %v0, 0, -1
-	wclfeb	%v0, %v0, 0, 16
-	wclfeb	%v0, %v0, -1, 0
-	wclfeb	%v0, %v0, 16, 0
-

Copied: llvm/trunk/test/MC/SystemZ/insn-bad-z15.s (from r372434, llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z15.s?p2=llvm/trunk/test/MC/SystemZ/insn-bad-z15.s&p1=llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s&r1=372434&r2=372435&rev=372435&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-arch13.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z15.s Fri Sep 20 16:04:45 2019
@@ -1,4 +1,6 @@
-# For arch13 only.
+# For z15 only.
+# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z15 < %s 2> %t
+# RUN: FileCheck < %t %s
 # RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch13 < %s 2> %t
 # RUN: FileCheck < %t %s
 

Removed: llvm/trunk/test/MC/SystemZ/insn-good-arch13.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-arch13.s?rev=372434&view=auto
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-arch13.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-arch13.s (removed)
@@ -1,1344 +0,0 @@
-# For arch13 and above.
-# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch13 -show-encoding %s \
-# RUN:   | FileCheck %s
-
-#CHECK: dfltcc	%r2, %r2, %r2           # encoding: [0xb9,0x39,0x20,0x22]
-#CHECK: dfltcc	%r2, %r8, %r15          # encoding: [0xb9,0x39,0xf0,0x28]
-#CHECK: dfltcc	%r14, %r8, %r2          # encoding: [0xb9,0x39,0x20,0xe8]
-#CHECK: dfltcc	%r6, %r8, %r10          # encoding: [0xb9,0x39,0xa0,0x68]
-
-	dfltcc	%r2, %r2, %r2
-	dfltcc	%r2, %r8, %r15
-	dfltcc	%r14, %r8, %r2
-	dfltcc	%r6, %r8, %r10
-
-#CHECK: kdsa	%r0, %r2                # encoding: [0xb9,0x3a,0x00,0x02]
-#CHECK: kdsa	%r0, %r14               # encoding: [0xb9,0x3a,0x00,0x0e]
-#CHECK: kdsa	%r15, %r2               # encoding: [0xb9,0x3a,0x00,0xf2]
-#CHECK: kdsa	%r7, %r10               # encoding: [0xb9,0x3a,0x00,0x7a]
-
-	kdsa	%r0, %r2
-	kdsa	%r0, %r14
-	kdsa	%r15, %r2
-	kdsa	%r7, %r10
-
-#CHECK: vllebrzg %v0, 0                 # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
-#CHECK: vllebrzg %v0, 4095              # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
-#CHECK: vllebrzg %v0, 0(%r15)           # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x04]
-#CHECK: vllebrzg %v0, 0(%r15,%r1)       # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x04]
-#CHECK: vllebrzg %v15, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x04]
-#CHECK: vllebrzg %v31, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
-#CHECK: vllebrzg %v18, 1383(%r3,%r4)    # encoding: [0xe6,0x23,0x45,0x67,0x38,0x04]
-
-	ldrv	%f0, 0
-	ldrv	%f0, 4095
-	ldrv	%f0, 0(%r15)
-	ldrv	%f0, 0(%r15,%r1)
-	ldrv	%f15, 0
-	ldrv	%v31, 0
-	ldrv	%v18, 0x567(%r3,%r4)
-
-#CHECK: vllebrze %v0, 0                 # encoding: [0xe6,0x00,0x00,0x00,0x60,0x04]
-#CHECK: vllebrze %v0, 4095              # encoding: [0xe6,0x00,0x0f,0xff,0x60,0x04]
-#CHECK: vllebrze %v0, 0(%r15)           # encoding: [0xe6,0x00,0xf0,0x00,0x60,0x04]
-#CHECK: vllebrze %v0, 0(%r15,%r1)       # encoding: [0xe6,0x0f,0x10,0x00,0x60,0x04]
-#CHECK: vllebrze %v15, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x60,0x04]
-#CHECK: vllebrze %v31, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x68,0x04]
-#CHECK: vllebrze %v18, 1383(%r3,%r4)    # encoding: [0xe6,0x23,0x45,0x67,0x68,0x04]
-
-	lerv	%f0, 0
-	lerv	%f0, 4095
-	lerv	%f0, 0(%r15)
-	lerv	%f0, 0(%r15,%r1)
-	lerv	%f15, 0
-	lerv	%v31, 0
-	lerv	%v18, 0x567(%r3,%r4)
-
-#CHECK: mvcrl	0, 0                    # encoding: [0xe5,0x0a,0x00,0x00,0x00,0x00]
-#CHECK: mvcrl	0(%r1), 0(%r2)          # encoding: [0xe5,0x0a,0x10,0x00,0x20,0x00]
-#CHECK: mvcrl	160(%r1), 320(%r15)     # encoding: [0xe5,0x0a,0x10,0xa0,0xf1,0x40]
-#CHECK: mvcrl	0(%r1), 4095            # encoding: [0xe5,0x0a,0x10,0x00,0x0f,0xff]
-#CHECK: mvcrl	0(%r1), 4095(%r2)       # encoding: [0xe5,0x0a,0x10,0x00,0x2f,0xff]
-#CHECK: mvcrl	0(%r1), 4095(%r15)      # encoding: [0xe5,0x0a,0x10,0x00,0xff,0xff]
-#CHECK: mvcrl	0(%r1), 0               # encoding: [0xe5,0x0a,0x10,0x00,0x00,0x00]
-#CHECK: mvcrl	0(%r15), 0              # encoding: [0xe5,0x0a,0xf0,0x00,0x00,0x00]
-#CHECK: mvcrl	4095(%r1), 0            # encoding: [0xe5,0x0a,0x1f,0xff,0x00,0x00]
-#CHECK: mvcrl	4095(%r15), 0           # encoding: [0xe5,0x0a,0xff,0xff,0x00,0x00]
-
-	mvcrl	0, 0
-	mvcrl	0(%r1), 0(%r2)
-	mvcrl	160(%r1), 320(%r15)
-	mvcrl	0(%r1), 4095
-	mvcrl	0(%r1), 4095(%r2)
-	mvcrl	0(%r1), 4095(%r15)
-	mvcrl	0(%r1), 0
-	mvcrl	0(%r15), 0
-	mvcrl	4095(%r1), 0
-	mvcrl	4095(%r15), 0
-
-#CHECK: ncgrk	%r0, %r0, %r0           # encoding: [0xb9,0xe5,0x00,0x00]
-#CHECK: ncgrk	%r0, %r0, %r15          # encoding: [0xb9,0xe5,0xf0,0x00]
-#CHECK: ncgrk	%r0, %r15, %r0          # encoding: [0xb9,0xe5,0x00,0x0f]
-#CHECK: ncgrk	%r15, %r0, %r0          # encoding: [0xb9,0xe5,0x00,0xf0]
-#CHECK: ncgrk	%r7, %r8, %r9           # encoding: [0xb9,0xe5,0x90,0x78]
-
-	ncgrk	%r0,%r0,%r0
-	ncgrk	%r0,%r0,%r15
-	ncgrk	%r0,%r15,%r0
-	ncgrk	%r15,%r0,%r0
-	ncgrk	%r7,%r8,%r9
-
-#CHECK: ncrk	%r0, %r0, %r0           # encoding: [0xb9,0xf5,0x00,0x00]
-#CHECK: ncrk	%r0, %r0, %r15          # encoding: [0xb9,0xf5,0xf0,0x00]
-#CHECK: ncrk	%r0, %r15, %r0          # encoding: [0xb9,0xf5,0x00,0x0f]
-#CHECK: ncrk	%r15, %r0, %r0          # encoding: [0xb9,0xf5,0x00,0xf0]
-#CHECK: ncrk	%r7, %r8, %r9           # encoding: [0xb9,0xf5,0x90,0x78]
-
-	ncrk	%r0,%r0,%r0
-	ncrk	%r0,%r0,%r15
-	ncrk	%r0,%r15,%r0
-	ncrk	%r15,%r0,%r0
-	ncrk	%r7,%r8,%r9
-
-#CHECK: nngrk	%r0, %r0, %r0           # encoding: [0xb9,0x64,0x00,0x00]
-#CHECK: nngrk	%r0, %r0, %r15          # encoding: [0xb9,0x64,0xf0,0x00]
-#CHECK: nngrk	%r0, %r15, %r0          # encoding: [0xb9,0x64,0x00,0x0f]
-#CHECK: nngrk	%r15, %r0, %r0          # encoding: [0xb9,0x64,0x00,0xf0]
-#CHECK: nngrk	%r7, %r8, %r9           # encoding: [0xb9,0x64,0x90,0x78]
-
-	nngrk	%r0,%r0,%r0
-	nngrk	%r0,%r0,%r15
-	nngrk	%r0,%r15,%r0
-	nngrk	%r15,%r0,%r0
-	nngrk	%r7,%r8,%r9
-
-#CHECK: nnrk	%r0, %r0, %r0           # encoding: [0xb9,0x74,0x00,0x00]
-#CHECK: nnrk	%r0, %r0, %r15          # encoding: [0xb9,0x74,0xf0,0x00]
-#CHECK: nnrk	%r0, %r15, %r0          # encoding: [0xb9,0x74,0x00,0x0f]
-#CHECK: nnrk	%r15, %r0, %r0          # encoding: [0xb9,0x74,0x00,0xf0]
-#CHECK: nnrk	%r7, %r8, %r9           # encoding: [0xb9,0x74,0x90,0x78]
-
-	nnrk	%r0,%r0,%r0
-	nnrk	%r0,%r0,%r15
-	nnrk	%r0,%r15,%r0
-	nnrk	%r15,%r0,%r0
-	nnrk	%r7,%r8,%r9
-
-#CHECK: nogrk	%r0, %r0, %r0           # encoding: [0xb9,0x66,0x00,0x00]
-#CHECK: nogrk	%r0, %r0, %r15          # encoding: [0xb9,0x66,0xf0,0x00]
-#CHECK: nogrk	%r0, %r15, %r0          # encoding: [0xb9,0x66,0x00,0x0f]
-#CHECK: nogrk	%r15, %r0, %r0          # encoding: [0xb9,0x66,0x00,0xf0]
-#CHECK: nogrk	%r7, %r8, %r9           # encoding: [0xb9,0x66,0x90,0x78]
-
-	nogrk	%r0,%r0,%r0
-	nogrk	%r0,%r0,%r15
-	nogrk	%r0,%r15,%r0
-	nogrk	%r15,%r0,%r0
-	nogrk	%r7,%r8,%r9
-
-#CHECK: nork	%r0, %r0, %r0           # encoding: [0xb9,0x76,0x00,0x00]
-#CHECK: nork	%r0, %r0, %r15          # encoding: [0xb9,0x76,0xf0,0x00]
-#CHECK: nork	%r0, %r15, %r0          # encoding: [0xb9,0x76,0x00,0x0f]
-#CHECK: nork	%r15, %r0, %r0          # encoding: [0xb9,0x76,0x00,0xf0]
-#CHECK: nork	%r7, %r8, %r9           # encoding: [0xb9,0x76,0x90,0x78]
-
-	nork	%r0,%r0,%r0
-	nork	%r0,%r0,%r15
-	nork	%r0,%r15,%r0
-	nork	%r15,%r0,%r0
-	nork	%r7,%r8,%r9
-
-#CHECK: nxgrk	%r0, %r0, %r0           # encoding: [0xb9,0x67,0x00,0x00]
-#CHECK: nxgrk	%r0, %r0, %r15          # encoding: [0xb9,0x67,0xf0,0x00]
-#CHECK: nxgrk	%r0, %r15, %r0          # encoding: [0xb9,0x67,0x00,0x0f]
-#CHECK: nxgrk	%r15, %r0, %r0          # encoding: [0xb9,0x67,0x00,0xf0]
-#CHECK: nxgrk	%r7, %r8, %r9           # encoding: [0xb9,0x67,0x90,0x78]
-
-	nxgrk	%r0,%r0,%r0
-	nxgrk	%r0,%r0,%r15
-	nxgrk	%r0,%r15,%r0
-	nxgrk	%r15,%r0,%r0
-	nxgrk	%r7,%r8,%r9
-
-#CHECK: nxrk	%r0, %r0, %r0           # encoding: [0xb9,0x77,0x00,0x00]
-#CHECK: nxrk	%r0, %r0, %r15          # encoding: [0xb9,0x77,0xf0,0x00]
-#CHECK: nxrk	%r0, %r15, %r0          # encoding: [0xb9,0x77,0x00,0x0f]
-#CHECK: nxrk	%r15, %r0, %r0          # encoding: [0xb9,0x77,0x00,0xf0]
-#CHECK: nxrk	%r7, %r8, %r9           # encoding: [0xb9,0x77,0x90,0x78]
-
-	nxrk	%r0,%r0,%r0
-	nxrk	%r0,%r0,%r15
-	nxrk	%r0,%r15,%r0
-	nxrk	%r15,%r0,%r0
-	nxrk	%r7,%r8,%r9
-
-#CHECK: ocgrk	%r0, %r0, %r0           # encoding: [0xb9,0x65,0x00,0x00]
-#CHECK: ocgrk	%r0, %r0, %r15          # encoding: [0xb9,0x65,0xf0,0x00]
-#CHECK: ocgrk	%r0, %r15, %r0          # encoding: [0xb9,0x65,0x00,0x0f]
-#CHECK: ocgrk	%r15, %r0, %r0          # encoding: [0xb9,0x65,0x00,0xf0]
-#CHECK: ocgrk	%r7, %r8, %r9           # encoding: [0xb9,0x65,0x90,0x78]
-
-	ocgrk	%r0,%r0,%r0
-	ocgrk	%r0,%r0,%r15
-	ocgrk	%r0,%r15,%r0
-	ocgrk	%r15,%r0,%r0
-	ocgrk	%r7,%r8,%r9
-
-#CHECK: ocrk	%r0, %r0, %r0           # encoding: [0xb9,0x75,0x00,0x00]
-#CHECK: ocrk	%r0, %r0, %r15          # encoding: [0xb9,0x75,0xf0,0x00]
-#CHECK: ocrk	%r0, %r15, %r0          # encoding: [0xb9,0x75,0x00,0x0f]
-#CHECK: ocrk	%r15, %r0, %r0          # encoding: [0xb9,0x75,0x00,0xf0]
-#CHECK: ocrk	%r7, %r8, %r9           # encoding: [0xb9,0x75,0x90,0x78]
-
-	ocrk	%r0,%r0,%r0
-	ocrk	%r0,%r0,%r15
-	ocrk	%r0,%r15,%r0
-	ocrk	%r15,%r0,%r0
-	ocrk	%r7,%r8,%r9
-
-#CHECK: popcnt	%r0, %r0                # encoding: [0xb9,0xe1,0x00,0x00]
-#CHECK: popcnt	%r0, %r15               # encoding: [0xb9,0xe1,0x00,0x0f]
-#CHECK: popcnt	%r14, %r0               # encoding: [0xb9,0xe1,0x00,0xe0]
-#CHECK: popcnt	%r6, %r8                # encoding: [0xb9,0xe1,0x00,0x68]
-#CHECK: popcnt	%r4, %r13, 1            # encoding: [0xb9,0xe1,0x10,0x4d]
-#CHECK: popcnt	%r4, %r13, 15           # encoding: [0xb9,0xe1,0xf0,0x4d]
-
-	popcnt	%r0, %r0
-	popcnt	%r0, %r15
-	popcnt	%r14, %r0
-	popcnt	%r6, %r8
-	popcnt	%r4, %r13, 1
-	popcnt	%r4, %r13, 15
-
-#CHECK: selgr	%r0, %r0, %r0, 0        # encoding: [0xb9,0xe3,0x00,0x00]
-#CHECK: selgr	%r0, %r0, %r0, 15       # encoding: [0xb9,0xe3,0x0f,0x00]
-#CHECK: selgr	%r0, %r0, %r15, 0       # encoding: [0xb9,0xe3,0xf0,0x00]
-#CHECK: selgr	%r0, %r15, %r0, 0       # encoding: [0xb9,0xe3,0x00,0x0f]
-#CHECK: selgr	%r15, %r0, %r0, 0       # encoding: [0xb9,0xe3,0x00,0xf0]
-#CHECK: selgr	%r7, %r8, %r9, 10       # encoding: [0xb9,0xe3,0x9a,0x78]
-
-	selgr	%r0, %r0, %r0, 0
-	selgr	%r0, %r0, %r0, 15
-	selgr	%r0, %r0, %r15, 0
-	selgr	%r0, %r15, %r0, 0
-	selgr	%r15, %r0, %r0, 0
-	selgr	%r7, %r8, %r9, 10
-
-#CHECK: selgro   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x31,0x12]
-#CHECK: selgrh   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x32,0x12]
-#CHECK: selgrp   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x32,0x12]
-#CHECK: selgrnle %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x33,0x12]
-#CHECK: selgrl   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x34,0x12]
-#CHECK: selgrm   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x34,0x12]
-#CHECK: selgrnhe %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x35,0x12]
-#CHECK: selgrlh  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x36,0x12]
-#CHECK: selgrne  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x37,0x12]
-#CHECK: selgrnz  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x37,0x12]
-#CHECK: selgre   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x38,0x12]
-#CHECK: selgrz   %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x38,0x12]
-#CHECK: selgrnlh %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x39,0x12]
-#CHECK: selgrhe  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3a,0x12]
-#CHECK: selgrnl  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3b,0x12]
-#CHECK: selgrnm  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3b,0x12]
-#CHECK: selgrle  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3c,0x12]
-#CHECK: selgrnh  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3d,0x12]
-#CHECK: selgrnp  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3d,0x12]
-#CHECK: selgrno  %r1, %r2, %r3          # encoding: [0xb9,0xe3,0x3e,0x12]
-
-	selgro   %r1, %r2, %r3
-	selgrh   %r1, %r2, %r3
-	selgrp   %r1, %r2, %r3
-	selgrnle %r1, %r2, %r3
-	selgrl   %r1, %r2, %r3
-	selgrm   %r1, %r2, %r3
-	selgrnhe %r1, %r2, %r3
-	selgrlh  %r1, %r2, %r3
-	selgrne  %r1, %r2, %r3
-	selgrnz  %r1, %r2, %r3
-	selgre   %r1, %r2, %r3
-	selgrz   %r1, %r2, %r3
-	selgrnlh %r1, %r2, %r3
-	selgrhe  %r1, %r2, %r3
-	selgrnl  %r1, %r2, %r3
-	selgrnm  %r1, %r2, %r3
-	selgrle  %r1, %r2, %r3
-	selgrnh  %r1, %r2, %r3
-	selgrnp  %r1, %r2, %r3
-	selgrno  %r1, %r2, %r3
-
-#CHECK: selfhr	%r0, %r0, %r0, 0         # encoding: [0xb9,0xc0,0x00,0x00]
-#CHECK: selfhr	%r0, %r0, %r0, 15        # encoding: [0xb9,0xc0,0x0f,0x00]
-#CHECK: selfhr	%r0, %r0, %r15, 0        # encoding: [0xb9,0xc0,0xf0,0x00]
-#CHECK: selfhr	%r0, %r15, %r0, 0        # encoding: [0xb9,0xc0,0x00,0x0f]
-#CHECK: selfhr	%r15, %r0, %r0, 0        # encoding: [0xb9,0xc0,0x00,0xf0]
-#CHECK: selfhr	%r7, %r8, %r9, 10        # encoding: [0xb9,0xc0,0x9a,0x78]
-
-	selfhr	%r0, %r0, %r0, 0
-	selfhr	%r0, %r0, %r0, 15
-	selfhr	%r0, %r0, %r15, 0
-	selfhr	%r0, %r15, %r0, 0
-	selfhr	%r15, %r0, %r0, 0
-	selfhr	%r7, %r8, %r9, 10
-
-#CHECK: selfhro   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x31,0x12]
-#CHECK: selfhrh   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x32,0x12]
-#CHECK: selfhrp   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x32,0x12]
-#CHECK: selfhrnle %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x33,0x12]
-#CHECK: selfhrl   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x34,0x12]
-#CHECK: selfhrm   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x34,0x12]
-#CHECK: selfhrnhe %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x35,0x12]
-#CHECK: selfhrlh  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x36,0x12]
-#CHECK: selfhrne  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x37,0x12]
-#CHECK: selfhrnz  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x37,0x12]
-#CHECK: selfhre   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x38,0x12]
-#CHECK: selfhrz   %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x38,0x12]
-#CHECK: selfhrnlh %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x39,0x12]
-#CHECK: selfhrhe  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3a,0x12]
-#CHECK: selfhrnl  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3b,0x12]
-#CHECK: selfhrnm  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3b,0x12]
-#CHECK: selfhrle  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3c,0x12]
-#CHECK: selfhrnh  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3d,0x12]
-#CHECK: selfhrnp  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3d,0x12]
-#CHECK: selfhrno  %r1, %r2, %r3         # encoding: [0xb9,0xc0,0x3e,0x12]
-
-	selfhro   %r1, %r2, %r3
-	selfhrh   %r1, %r2, %r3
-	selfhrp   %r1, %r2, %r3
-	selfhrnle %r1, %r2, %r3
-	selfhrl   %r1, %r2, %r3
-	selfhrm   %r1, %r2, %r3
-	selfhrnhe %r1, %r2, %r3
-	selfhrlh  %r1, %r2, %r3
-	selfhrne  %r1, %r2, %r3
-	selfhrnz  %r1, %r2, %r3
-	selfhre   %r1, %r2, %r3
-	selfhrz   %r1, %r2, %r3
-	selfhrnlh %r1, %r2, %r3
-	selfhrhe  %r1, %r2, %r3
-	selfhrnl  %r1, %r2, %r3
-	selfhrnm  %r1, %r2, %r3
-	selfhrle  %r1, %r2, %r3
-	selfhrnh  %r1, %r2, %r3
-	selfhrnp  %r1, %r2, %r3
-	selfhrno  %r1, %r2, %r3
-
-#CHECK: selr	%r0, %r0, %r0, 0        # encoding: [0xb9,0xf0,0x00,0x00]
-#CHECK: selr	%r0, %r0, %r0, 15       # encoding: [0xb9,0xf0,0x0f,0x00]
-#CHECK: selr	%r0, %r0, %r15, 0       # encoding: [0xb9,0xf0,0xf0,0x00]
-#CHECK: selr	%r0, %r15, %r0, 0       # encoding: [0xb9,0xf0,0x00,0x0f]
-#CHECK: selr	%r15, %r0, %r0, 0       # encoding: [0xb9,0xf0,0x00,0xf0]
-#CHECK: selr	%r7, %r8, %r9, 10       # encoding: [0xb9,0xf0,0x9a,0x78]
-
-	selr	%r0, %r0, %r0, 0
-	selr	%r0, %r0, %r0, 15
-	selr	%r0, %r0, %r15, 0
-	selr	%r0, %r15, %r0, 0
-	selr	%r15, %r0, %r0, 0
-	selr	%r7, %r8, %r9, 10
-
-#CHECK: selro   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x31,0x12]
-#CHECK: selrh   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x32,0x12]
-#CHECK: selrp   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x32,0x12]
-#CHECK: selrnle %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x33,0x12]
-#CHECK: selrl   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x34,0x12]
-#CHECK: selrm   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x34,0x12]
-#CHECK: selrnhe %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x35,0x12]
-#CHECK: selrlh  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x36,0x12]
-#CHECK: selrne  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x37,0x12]
-#CHECK: selrnz  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x37,0x12]
-#CHECK: selre   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x38,0x12]
-#CHECK: selrz   %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x38,0x12]
-#CHECK: selrnlh %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x39,0x12]
-#CHECK: selrhe  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3a,0x12]
-#CHECK: selrnl  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3b,0x12]
-#CHECK: selrnm  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3b,0x12]
-#CHECK: selrle  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3c,0x12]
-#CHECK: selrnh  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3d,0x12]
-#CHECK: selrnp  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3d,0x12]
-#CHECK: selrno  %r1, %r2, %r3           # encoding: [0xb9,0xf0,0x3e,0x12]
-
-	selro   %r1, %r2, %r3
-	selrh   %r1, %r2, %r3
-	selrp   %r1, %r2, %r3
-	selrnle %r1, %r2, %r3
-	selrl   %r1, %r2, %r3
-	selrm   %r1, %r2, %r3
-	selrnhe %r1, %r2, %r3
-	selrlh  %r1, %r2, %r3
-	selrne  %r1, %r2, %r3
-	selrnz  %r1, %r2, %r3
-	selre   %r1, %r2, %r3
-	selrz   %r1, %r2, %r3
-	selrnlh %r1, %r2, %r3
-	selrhe  %r1, %r2, %r3
-	selrnl  %r1, %r2, %r3
-	selrnm  %r1, %r2, %r3
-	selrle  %r1, %r2, %r3
-	selrnh  %r1, %r2, %r3
-	selrnp  %r1, %r2, %r3
-	selrno  %r1, %r2, %r3
-
-#CHECK: sortl	%r2, %r2                # encoding: [0xb9,0x38,0x00,0x22]
-#CHECK: sortl	%r2, %r14               # encoding: [0xb9,0x38,0x00,0x2e]
-#CHECK: sortl	%r14, %r2               # encoding: [0xb9,0x38,0x00,0xe2]
-#CHECK: sortl	%r6, %r10               # encoding: [0xb9,0x38,0x00,0x6a]
-
-	sortl	%r2, %r2
-	sortl	%r2, %r14
-	sortl	%r14, %r2
-	sortl	%r6, %r10
-
-#CHECK: vstebrg %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x0a]
-#CHECK: vstebrg %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x0a]
-#CHECK: vstebrg %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x0a]
-#CHECK: vstebrg %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x0a]
-#CHECK: vstebrg %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x0a]
-#CHECK: vstebrg %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0a]
-#CHECK: vstebrg %v18, 1383(%r3,%r4), 0  # encoding: [0xe6,0x23,0x45,0x67,0x08,0x0a]
-
-	stdrv	%f0, 0
-	stdrv	%f0, 4095
-	stdrv	%f0, 0(%r15)
-	stdrv	%f0, 0(%r15,%r1)
-	stdrv	%f15, 0
-	stdrv	%v31, 0
-	stdrv	%v18, 0x567(%r3,%r4)
-
-#CHECK: vstebrf %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x0b]
-#CHECK: vstebrf %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x0b]
-#CHECK: vstebrf %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x0b]
-#CHECK: vstebrf %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x0b]
-#CHECK: vstebrf %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x0b]
-#CHECK: vstebrf %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0b]
-#CHECK: vstebrf %v18, 1383(%r3,%r4), 0  # encoding: [0xe6,0x23,0x45,0x67,0x08,0x0b]
-
-	sterv	%f0, 0
-	sterv	%f0, 4095
-	sterv	%f0, 0(%r15)
-	sterv	%f0, 0(%r15,%r1)
-	sterv	%f15, 0
-	sterv	%v31, 0
-	sterv	%v18, 0x567(%r3,%r4)
-
-#CHECK: vcefb   %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x20,0xc3]
-#CHECK: vcefb   %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x20,0xc3]
-#CHECK: vcefb   %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x20,0xc3]
-#CHECK: vcefb   %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc3]
-#CHECK: vcefb   %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc3]
-#CHECK: vcefb   %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xc3]
-#CHECK: vcefb   %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x24,0xc3]
-
-	vcefb	%v0, %v0, 0, 0
-	vcefb	%v0, %v0, 0, 15
-	vcefb	%v0, %v0, 4, 0
-	vcefb	%v0, %v0, 12, 0
-	vcefb	%v0, %v31, 0, 0
-	vcefb	%v31, %v0, 0, 0
-	vcefb	%v14, %v17, 4, 10
-
-#CHECK: vcelfb  %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x20,0xc1]
-#CHECK: vcelfb  %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x20,0xc1]
-#CHECK: vcelfb  %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x20,0xc1]
-#CHECK: vcelfb  %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc1]
-#CHECK: vcelfb  %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc1]
-#CHECK: vcelfb  %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xc1]
-#CHECK: vcelfb  %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x24,0xc1]
-
-	vcelfb	%v0, %v0, 0, 0
-	vcelfb	%v0, %v0, 0, 15
-	vcelfb	%v0, %v0, 4, 0
-	vcelfb	%v0, %v0, 12, 0
-	vcelfb	%v0, %v31, 0, 0
-	vcelfb	%v31, %v0, 0, 0
-	vcelfb	%v14, %v17, 4, 10
-
-#CHECK: vcfeb   %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x20,0xc2]
-#CHECK: vcfeb   %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x20,0xc2]
-#CHECK: vcfeb   %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x20,0xc2]
-#CHECK: vcfeb   %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc2]
-#CHECK: vcfeb   %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc2]
-#CHECK: vcfeb   %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xc2]
-#CHECK: vcfeb   %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x24,0xc2]
-
-	vcfeb	%v0, %v0, 0, 0
-	vcfeb	%v0, %v0, 0, 15
-	vcfeb	%v0, %v0, 4, 0
-	vcfeb	%v0, %v0, 12, 0
-	vcfeb	%v0, %v31, 0, 0
-	vcfeb	%v31, %v0, 0, 0
-	vcfeb	%v14, %v17, 4, 10
-
-#CHECK: vcfpl   %v0, %v0, 0, 0, 0       # encoding: [0xe7,0x00,0x00,0x00,0x00,0xc1]
-#CHECK: vcfpl   %v0, %v0, 15, 0, 0      # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xc1]
-#CHECK: vcfpl   %v0, %v0, 0, 0, 15      # encoding: [0xe7,0x00,0x00,0xf0,0x00,0xc1]
-#CHECK: vcfpl   %v0, %v0, 0, 4, 0       # encoding: [0xe7,0x00,0x00,0x04,0x00,0xc1]
-#CHECK: vcfpl   %v0, %v0, 0, 12, 0      # encoding: [0xe7,0x00,0x00,0x0c,0x00,0xc1]
-#CHECK: vcfpl   %v0, %v31, 0, 0, 0      # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xc1]
-#CHECK: vcfpl   %v31, %v0, 0, 0, 0      # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xc1]
-#CHECK: vcfpl   %v14, %v17, 11, 4, 10   # encoding: [0xe7,0xe1,0x00,0xa4,0xb4,0xc1]
-
-	vcfpl	%v0, %v0, 0, 0, 0
-	vcfpl	%v0, %v0, 15, 0, 0
-	vcfpl	%v0, %v0, 0, 0, 15
-	vcfpl	%v0, %v0, 0, 4, 0
-	vcfpl	%v0, %v0, 0, 12, 0
-	vcfpl	%v0, %v31, 0, 0, 0
-	vcfpl	%v31, %v0, 0, 0, 0
-	vcfpl	%v14, %v17, 11, 4, 10
-
-#CHECK: vcfps   %v0, %v0, 0, 0, 0       # encoding: [0xe7,0x00,0x00,0x00,0x00,0xc3]
-#CHECK: vcfps   %v0, %v0, 15, 0, 0      # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xc3]
-#CHECK: vcfps   %v0, %v0, 0, 0, 15      # encoding: [0xe7,0x00,0x00,0xf0,0x00,0xc3]
-#CHECK: vcfps   %v0, %v0, 0, 4, 0       # encoding: [0xe7,0x00,0x00,0x04,0x00,0xc3]
-#CHECK: vcfps   %v0, %v0, 0, 12, 0      # encoding: [0xe7,0x00,0x00,0x0c,0x00,0xc3]
-#CHECK: vcfps   %v0, %v31, 0, 0, 0      # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xc3]
-#CHECK: vcfps   %v31, %v0, 0, 0, 0      # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xc3]
-#CHECK: vcfps   %v14, %v17, 11, 4, 10   # encoding: [0xe7,0xe1,0x00,0xa4,0xb4,0xc3]
-
-	vcfps	%v0, %v0, 0, 0, 0
-	vcfps	%v0, %v0, 15, 0, 0
-	vcfps	%v0, %v0, 0, 0, 15
-	vcfps	%v0, %v0, 0, 4, 0
-	vcfps	%v0, %v0, 0, 12, 0
-	vcfps	%v0, %v31, 0, 0, 0
-	vcfps	%v31, %v0, 0, 0, 0
-	vcfps	%v14, %v17, 11, 4, 10
-
-#CHECK: vclfeb  %v0, %v0, 0, 0          # encoding: [0xe7,0x00,0x00,0x00,0x20,0xc0]
-#CHECK: vclfeb  %v0, %v0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf0,0x20,0xc0]
-#CHECK: vclfeb  %v0, %v0, 4, 0          # encoding: [0xe7,0x00,0x00,0x04,0x20,0xc0]
-#CHECK: vclfeb  %v0, %v0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc0]
-#CHECK: vclfeb  %v0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x00,0x24,0xc0]
-#CHECK: vclfeb  %v31, %v0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x00,0x28,0xc0]
-#CHECK: vclfeb  %v14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xa4,0x24,0xc0]
-
-	vclfeb	%v0, %v0, 0, 0
-	vclfeb	%v0, %v0, 0, 15
-	vclfeb	%v0, %v0, 4, 0
-	vclfeb	%v0, %v0, 12, 0
-	vclfeb	%v0, %v31, 0, 0
-	vclfeb	%v31, %v0, 0, 0
-	vclfeb	%v14, %v17, 4, 10
-
-#CHECK: vclfp   %v0, %v0, 0, 0, 0       # encoding: [0xe7,0x00,0x00,0x00,0x00,0xc0]
-#CHECK: vclfp   %v0, %v0, 15, 0, 0      # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xc0]
-#CHECK: vclfp   %v0, %v0, 0, 0, 15      # encoding: [0xe7,0x00,0x00,0xf0,0x00,0xc0]
-#CHECK: vclfp   %v0, %v0, 0, 4, 0       # encoding: [0xe7,0x00,0x00,0x04,0x00,0xc0]
-#CHECK: vclfp   %v0, %v0, 0, 12, 0      # encoding: [0xe7,0x00,0x00,0x0c,0x00,0xc0]
-#CHECK: vclfp   %v0, %v31, 0, 0, 0      # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xc0]
-#CHECK: vclfp   %v31, %v0, 0, 0, 0      # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xc0]
-#CHECK: vclfp   %v14, %v17, 11, 4, 10   # encoding: [0xe7,0xe1,0x00,0xa4,0xb4,0xc0]
-
-	vclfp	%v0, %v0, 0, 0, 0
-	vclfp	%v0, %v0, 15, 0, 0
-	vclfp	%v0, %v0, 0, 0, 15
-	vclfp	%v0, %v0, 0, 4, 0
-	vclfp	%v0, %v0, 0, 12, 0
-	vclfp	%v0, %v31, 0, 0, 0
-	vclfp	%v31, %v0, 0, 0, 0
-	vclfp	%v14, %v17, 11, 4, 10
-
-#CHECK: vcsfp   %v0, %v0, 0, 0, 0       # encoding: [0xe7,0x00,0x00,0x00,0x00,0xc2]
-#CHECK: vcsfp   %v0, %v0, 15, 0, 0      # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xc2]
-#CHECK: vcsfp   %v0, %v0, 0, 0, 15      # encoding: [0xe7,0x00,0x00,0xf0,0x00,0xc2]
-#CHECK: vcsfp   %v0, %v0, 0, 4, 0       # encoding: [0xe7,0x00,0x00,0x04,0x00,0xc2]
-#CHECK: vcsfp   %v0, %v0, 0, 12, 0      # encoding: [0xe7,0x00,0x00,0x0c,0x00,0xc2]
-#CHECK: vcsfp   %v0, %v31, 0, 0, 0      # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xc2]
-#CHECK: vcsfp   %v31, %v0, 0, 0, 0      # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xc2]
-#CHECK: vcsfp   %v14, %v17, 11, 4, 10   # encoding: [0xe7,0xe1,0x00,0xa4,0xb4,0xc2]
-
-	vcsfp	%v0, %v0, 0, 0, 0
-	vcsfp	%v0, %v0, 15, 0, 0
-	vcsfp	%v0, %v0, 0, 0, 15
-	vcsfp	%v0, %v0, 0, 4, 0
-	vcsfp	%v0, %v0, 0, 12, 0
-	vcsfp	%v0, %v31, 0, 0, 0
-	vcsfp	%v31, %v0, 0, 0, 0
-	vcsfp	%v14, %v17, 11, 4, 10
-
-#CHECK: vcvb	%r0, %v0, 0, 15        # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x50]
-#CHECK: vcvb	%r3, %v18, 4, 6        # encoding: [0xe6,0x32,0x00,0x46,0x04,0x50]
-
-	vcvb	%r0, %v0, 0, 15
-	vcvb	%r3, %v18, 4, 6
-
-#CHECK: vcvbg	%r0, %v0, 0, 15        # encoding: [0xe6,0x00,0x00,0x0f,0x00,0x52]
-#CHECK: vcvbg	%r3, %v18, 4, 6        # encoding: [0xe6,0x32,0x00,0x46,0x04,0x52]
-
-	vcvbg	%r0, %v0, 0, 15
-	vcvbg	%r3, %v18, 4, 6
-
-#CHECK: vlbr   %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x06]
-#CHECK: vlbr   %v0, 0, 15              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x06]
-#CHECK: vlbr   %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x06]
-#CHECK: vlbr   %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x06]
-#CHECK: vlbr   %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x06]
-#CHECK: vlbr   %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x06]
-#CHECK: vlbr   %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x06]
-#CHECK: vlbr   %v18, 1383(%r3,%r4), 11 # encoding: [0xe6,0x23,0x45,0x67,0xb8,0x06]
-
-	vlbr	%v0, 0, 0
-	vlbr	%v0, 0, 15
-	vlbr	%v0, 4095, 0
-	vlbr	%v0, 0(%r15), 0
-	vlbr	%v0, 0(%r15,%r1), 0
-	vlbr	%v15, 0, 0
-	vlbr	%v31, 0, 0
-	vlbr	%v18, 0x567(%r3,%r4), 11
-
-#CHECK: vlbrf  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x20,0x06]
-#CHECK: vlbrf  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x20,0x06]
-#CHECK: vlbrf  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x06]
-#CHECK: vlbrf  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x20,0x06]
-#CHECK: vlbrf  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x06]
-#CHECK: vlbrf  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x06]
-#CHECK: vlbrf  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x28,0x06]
-
-	vlbrf	%v0, 0
-	vlbrf	%v0, 4095
-	vlbrf	%v0, 0(%r15)
-	vlbrf	%v0, 0(%r15,%r1)
-	vlbrf	%v15, 0
-	vlbrf	%v31, 0
-	vlbrf	%v18, 0x567(%r3,%r4)
-
-#CHECK: vlbrg  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x30,0x06]
-#CHECK: vlbrg  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x06]
-#CHECK: vlbrg  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x06]
-#CHECK: vlbrg  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x06]
-#CHECK: vlbrg  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x06]
-#CHECK: vlbrg  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x06]
-#CHECK: vlbrg  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x38,0x06]
-
-	vlbrg	%v0, 0
-	vlbrg	%v0, 4095
-	vlbrg	%v0, 0(%r15)
-	vlbrg	%v0, 0(%r15,%r1)
-	vlbrg	%v15, 0
-	vlbrg	%v31, 0
-	vlbrg	%v18, 0x567(%r3,%r4)
-
-#CHECK: vlbrh  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x10,0x06]
-#CHECK: vlbrh  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x10,0x06]
-#CHECK: vlbrh  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x10,0x06]
-#CHECK: vlbrh  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x10,0x06]
-#CHECK: vlbrh  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x10,0x06]
-#CHECK: vlbrh  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x18,0x06]
-#CHECK: vlbrh  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x18,0x06]
-
-	vlbrh	%v0, 0
-	vlbrh	%v0, 4095
-	vlbrh	%v0, 0(%r15)
-	vlbrh	%v0, 0(%r15,%r1)
-	vlbrh	%v15, 0
-	vlbrh	%v31, 0
-	vlbrh	%v18, 0x567(%r3,%r4)
-
-#CHECK: vlbrq  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x40,0x06]
-#CHECK: vlbrq  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x40,0x06]
-#CHECK: vlbrq  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x40,0x06]
-#CHECK: vlbrq  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x40,0x06]
-#CHECK: vlbrq  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x40,0x06]
-#CHECK: vlbrq  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x48,0x06]
-#CHECK: vlbrq  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x48,0x06]
-
-	vlbrq	%v0, 0
-	vlbrq	%v0, 4095
-	vlbrq	%v0, 0(%r15)
-	vlbrq	%v0, 0(%r15,%r1)
-	vlbrq	%v15, 0
-	vlbrq	%v31, 0
-	vlbrq	%v18, 0x567(%r3,%r4)
-
-#CHECK: vlbrrep %v0, 0, 0              # encoding: [0xe6,0x00,0x00,0x00,0x00,0x05]
-#CHECK: vlbrrep %v0, 0, 15             # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x05]
-#CHECK: vlbrrep %v0, 4095, 0           # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x05]
-#CHECK: vlbrrep %v0, 0(%r15), 0        # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x05]
-#CHECK: vlbrrep %v0, 0(%r15,%r1), 0    # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x05]
-#CHECK: vlbrrep %v15, 0, 0             # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x05]
-#CHECK: vlbrrep %v31, 0, 0             # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x05]
-#CHECK: vlbrrep %v18, 1383(%r3,%r4), 11 # encoding: [0xe6,0x23,0x45,0x67,0xb8,0x05]
-
-	vlbrrep  %v0, 0, 0
-	vlbrrep  %v0, 0, 15
-	vlbrrep  %v0, 4095, 0
-	vlbrrep  %v0, 0(%r15), 0
-	vlbrrep  %v0, 0(%r15,%r1), 0
-	vlbrrep  %v15, 0, 0
-	vlbrrep  %v31, 0, 0
-	vlbrrep  %v18, 0x567(%r3,%r4), 11
-
-#CHECK: vlbrrepf %v0, 0                # encoding: [0xe6,0x00,0x00,0x00,0x20,0x05]
-#CHECK: vlbrrepf %v0, 4095             # encoding: [0xe6,0x00,0x0f,0xff,0x20,0x05]
-#CHECK: vlbrrepf %v0, 0(%r15)          # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x05]
-#CHECK: vlbrrepf %v0, 0(%r15,%r1)      # encoding: [0xe6,0x0f,0x10,0x00,0x20,0x05]
-#CHECK: vlbrrepf %v15, 0               # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x05]
-#CHECK: vlbrrepf %v31, 0               # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x05]
-#CHECK: vlbrrepf %v18, 1383(%r3,%r4)   # encoding: [0xe6,0x23,0x45,0x67,0x28,0x05]
-
-	vlbrrepf %v0, 0
-	vlbrrepf %v0, 4095
-	vlbrrepf %v0, 0(%r15)
-	vlbrrepf %v0, 0(%r15,%r1)
-	vlbrrepf %v15, 0
-	vlbrrepf %v31, 0
-	vlbrrepf %v18, 0x567(%r3,%r4)
-
-#CHECK: vlbrrepg %v0, 0                # encoding: [0xe6,0x00,0x00,0x00,0x30,0x05]
-#CHECK: vlbrrepg %v0, 4095             # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x05]
-#CHECK: vlbrrepg %v0, 0(%r15)          # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x05]
-#CHECK: vlbrrepg %v0, 0(%r15,%r1)      # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x05]
-#CHECK: vlbrrepg %v15, 0               # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x05]
-#CHECK: vlbrrepg %v31, 0               # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x05]
-#CHECK: vlbrrepg %v18, 1383(%r3,%r4)   # encoding: [0xe6,0x23,0x45,0x67,0x38,0x05]
-
-	vlbrrepg %v0, 0
-	vlbrrepg %v0, 4095
-	vlbrrepg %v0, 0(%r15)
-	vlbrrepg %v0, 0(%r15,%r1)
-	vlbrrepg %v15, 0
-	vlbrrepg %v31, 0
-	vlbrrepg %v18, 0x567(%r3,%r4)
-
-#CHECK: vlbrreph %v0, 0                # encoding: [0xe6,0x00,0x00,0x00,0x10,0x05]
-#CHECK: vlbrreph %v0, 4095             # encoding: [0xe6,0x00,0x0f,0xff,0x10,0x05]
-#CHECK: vlbrreph %v0, 0(%r15)          # encoding: [0xe6,0x00,0xf0,0x00,0x10,0x05]
-#CHECK: vlbrreph %v0, 0(%r15,%r1)      # encoding: [0xe6,0x0f,0x10,0x00,0x10,0x05]
-#CHECK: vlbrreph %v15, 0               # encoding: [0xe6,0xf0,0x00,0x00,0x10,0x05]
-#CHECK: vlbrreph %v31, 0               # encoding: [0xe6,0xf0,0x00,0x00,0x18,0x05]
-#CHECK: vlbrreph %v18, 1383(%r3,%r4)   # encoding: [0xe6,0x23,0x45,0x67,0x18,0x05]
-
-	vlbrreph %v0, 0
-	vlbrreph %v0, 4095
-	vlbrreph %v0, 0(%r15)
-	vlbrreph %v0, 0(%r15,%r1)
-	vlbrreph %v15, 0
-	vlbrreph %v31, 0
-	vlbrreph %v18, 0x567(%r3,%r4)
-
-#CHECK: vlebrf  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x03]
-#CHECK: vlebrf  %v0, 0, 3               # encoding: [0xe6,0x00,0x00,0x00,0x30,0x03]
-#CHECK: vlebrf  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x03]
-#CHECK: vlebrf  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x03]
-#CHECK: vlebrf  %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x03]
-#CHECK: vlebrf  %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x03]
-#CHECK: vlebrf  %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x03]
-#CHECK: vlebrf  %v18, 1383(%r3,%r4), 2  # encoding: [0xe6,0x23,0x45,0x67,0x28,0x03]
-
-	vlebrf	%v0, 0, 0
-	vlebrf	%v0, 0, 3
-	vlebrf	%v0, 4095, 0
-	vlebrf	%v0, 0(%r15), 0
-	vlebrf	%v0, 0(%r15,%r1), 0
-	vlebrf	%v15, 0, 0
-	vlebrf	%v31, 0, 0
-	vlebrf	%v18, 1383(%r3,%r4), 2
-
-#CHECK: vlebrg  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x02]
-#CHECK: vlebrg  %v0, 0, 1               # encoding: [0xe6,0x00,0x00,0x00,0x10,0x02]
-#CHECK: vlebrg  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x02]
-#CHECK: vlebrg  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x02]
-#CHECK: vlebrg  %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x02]
-#CHECK: vlebrg  %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x02]
-#CHECK: vlebrg  %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x02]
-#CHECK: vlebrg  %v18, 1383(%r3,%r4), 1  # encoding: [0xe6,0x23,0x45,0x67,0x18,0x02]
-
-	vlebrg	%v0, 0, 0
-	vlebrg	%v0, 0, 1
-	vlebrg	%v0, 4095, 0
-	vlebrg	%v0, 0(%r15), 0
-	vlebrg	%v0, 0(%r15,%r1), 0
-	vlebrg	%v15, 0, 0
-	vlebrg	%v31, 0, 0
-	vlebrg	%v18, 1383(%r3,%r4), 1
-
-#CHECK: vlebrh  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x01]
-#CHECK: vlebrh  %v0, 0, 7               # encoding: [0xe6,0x00,0x00,0x00,0x70,0x01]
-#CHECK: vlebrh  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x01]
-#CHECK: vlebrh  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x01]
-#CHECK: vlebrh  %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x01]
-#CHECK: vlebrh  %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x01]
-#CHECK: vlebrh  %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x01]
-#CHECK: vlebrh  %v18, 1383(%r3,%r4), 4  # encoding: [0xe6,0x23,0x45,0x67,0x48,0x01]
-
-	vlebrh	%v0, 0, 0
-	vlebrh	%v0, 0, 7
-	vlebrh	%v0, 4095, 0
-	vlebrh	%v0, 0(%r15), 0
-	vlebrh	%v0, 0(%r15,%r1), 0
-	vlebrh	%v15, 0, 0
-	vlebrh	%v31, 0, 0
-	vlebrh	%v18, 1383(%r3,%r4), 4
-
-#CHECK: vler   %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x07]
-#CHECK: vler   %v0, 0, 15              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x07]
-#CHECK: vler   %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x07]
-#CHECK: vler   %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x07]
-#CHECK: vler   %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x07]
-#CHECK: vler   %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x07]
-#CHECK: vler   %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x07]
-#CHECK: vler   %v18, 1383(%r3,%r4), 11 # encoding: [0xe6,0x23,0x45,0x67,0xb8,0x07]
-
-	vler	%v0, 0, 0
-	vler	%v0, 0, 15
-	vler	%v0, 4095, 0
-	vler	%v0, 0(%r15), 0
-	vler	%v0, 0(%r15,%r1), 0
-	vler	%v15, 0, 0
-	vler	%v31, 0, 0
-	vler	%v18, 0x567(%r3,%r4), 11
-
-#CHECK: vlerf  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x20,0x07]
-#CHECK: vlerf  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x20,0x07]
-#CHECK: vlerf  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x07]
-#CHECK: vlerf  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x20,0x07]
-#CHECK: vlerf  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x07]
-#CHECK: vlerf  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x07]
-#CHECK: vlerf  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x28,0x07]
-
-	vlerf	%v0, 0
-	vlerf	%v0, 4095
-	vlerf	%v0, 0(%r15)
-	vlerf	%v0, 0(%r15,%r1)
-	vlerf	%v15, 0
-	vlerf	%v31, 0
-	vlerf	%v18, 0x567(%r3,%r4)
-
-#CHECK: vlerg  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x30,0x07]
-#CHECK: vlerg  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x07]
-#CHECK: vlerg  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x07]
-#CHECK: vlerg  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x07]
-#CHECK: vlerg  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x07]
-#CHECK: vlerg  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x07]
-#CHECK: vlerg  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x38,0x07]
-
-	vlerg	%v0, 0
-	vlerg	%v0, 4095
-	vlerg	%v0, 0(%r15)
-	vlerg	%v0, 0(%r15,%r1)
-	vlerg	%v15, 0
-	vlerg	%v31, 0
-	vlerg	%v18, 0x567(%r3,%r4)
-
-#CHECK: vlerh  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x10,0x07]
-#CHECK: vlerh  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x10,0x07]
-#CHECK: vlerh  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x10,0x07]
-#CHECK: vlerh  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x10,0x07]
-#CHECK: vlerh  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x10,0x07]
-#CHECK: vlerh  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x18,0x07]
-#CHECK: vlerh  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x18,0x07]
-
-	vlerh	%v0, 0
-	vlerh	%v0, 4095
-	vlerh	%v0, 0(%r15)
-	vlerh	%v0, 0(%r15,%r1)
-	vlerh	%v15, 0
-	vlerh	%v31, 0
-	vlerh	%v18, 0x567(%r3,%r4)
-
-#CHECK: vllebrz   %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x04]
-#CHECK: vllebrz   %v0, 0, 15              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x04]
-#CHECK: vllebrz   %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x04]
-#CHECK: vllebrz   %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x04]
-#CHECK: vllebrz   %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x04]
-#CHECK: vllebrz   %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x04]
-#CHECK: vllebrz   %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x04]
-#CHECK: vllebrz   %v18, 1383(%r3,%r4), 11 # encoding: [0xe6,0x23,0x45,0x67,0xb8,0x04]
-
-	vllebrz	%v0, 0, 0
-	vllebrz	%v0, 0, 15
-	vllebrz	%v0, 4095, 0
-	vllebrz	%v0, 0(%r15), 0
-	vllebrz	%v0, 0(%r15,%r1), 0
-	vllebrz	%v15, 0, 0
-	vllebrz	%v31, 0, 0
-	vllebrz	%v18, 0x567(%r3,%r4), 11
-
-#CHECK: vllebrze  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x60,0x04]
-#CHECK: vllebrze  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x60,0x04]
-#CHECK: vllebrze  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x60,0x04]
-#CHECK: vllebrze  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x60,0x04]
-#CHECK: vllebrze  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x60,0x04]
-#CHECK: vllebrze  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x68,0x04]
-#CHECK: vllebrze  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x68,0x04]
-
-	vllebrze	%v0, 0
-	vllebrze	%v0, 4095
-	vllebrze	%v0, 0(%r15)
-	vllebrze	%v0, 0(%r15,%r1)
-	vllebrze	%v15, 0
-	vllebrze	%v31, 0
-	vllebrze	%v18, 0x567(%r3,%r4)
-
-#CHECK: vllebrzf  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x20,0x04]
-#CHECK: vllebrzf  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x20,0x04]
-#CHECK: vllebrzf  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x04]
-#CHECK: vllebrzf  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x20,0x04]
-#CHECK: vllebrzf  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x04]
-#CHECK: vllebrzf  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x04]
-#CHECK: vllebrzf  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x28,0x04]
-
-	vllebrzf	%v0, 0
-	vllebrzf	%v0, 4095
-	vllebrzf	%v0, 0(%r15)
-	vllebrzf	%v0, 0(%r15,%r1)
-	vllebrzf	%v15, 0
-	vllebrzf	%v31, 0
-	vllebrzf	%v18, 0x567(%r3,%r4)
-
-#CHECK: vllebrzg  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
-#CHECK: vllebrzg  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
-#CHECK: vllebrzg  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x04]
-#CHECK: vllebrzg  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x04]
-#CHECK: vllebrzg  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x04]
-#CHECK: vllebrzg  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
-#CHECK: vllebrzg  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x38,0x04]
-
-	vllebrzg	%v0, 0
-	vllebrzg	%v0, 4095
-	vllebrzg	%v0, 0(%r15)
-	vllebrzg	%v0, 0(%r15,%r1)
-	vllebrzg	%v15, 0
-	vllebrzg	%v31, 0
-	vllebrzg	%v18, 0x567(%r3,%r4)
-
-#CHECK: vllebrzh  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x10,0x04]
-#CHECK: vllebrzh  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x10,0x04]
-#CHECK: vllebrzh  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x10,0x04]
-#CHECK: vllebrzh  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x10,0x04]
-#CHECK: vllebrzh  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x10,0x04]
-#CHECK: vllebrzh  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x18,0x04]
-#CHECK: vllebrzh  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x18,0x04]
-
-	vllebrzh	%v0, 0
-	vllebrzh	%v0, 4095
-	vllebrzh	%v0, 0(%r15)
-	vllebrzh	%v0, 0(%r15,%r1)
-	vllebrzh	%v15, 0
-	vllebrzh	%v31, 0
-	vllebrzh	%v18, 0x567(%r3,%r4)
-
-#CHECK: vsld    %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x86]
-#CHECK: vsld    %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x00,0x86]
-#CHECK: vsld    %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x86]
-#CHECK: vsld    %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x86]
-#CHECK: vsld    %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x86]
-#CHECK: vsld    %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x86]
-
-	vsld	%v0, %v0, %v0, 0
-	vsld	%v0, %v0, %v0, 255
-	vsld	%v0, %v0, %v31, 0
-	vsld	%v0, %v31, %v0, 0
-	vsld	%v31, %v0, %v0, 0
-	vsld 	%v13, %v17, %v21, 0x79
-
-#CHECK: vsrd    %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0x87]
-#CHECK: vsrd    %v0, %v0, %v0, 255      # encoding: [0xe7,0x00,0x00,0xff,0x00,0x87]
-#CHECK: vsrd    %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x87]
-#CHECK: vsrd    %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x87]
-#CHECK: vsrd    %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x87]
-#CHECK: vsrd    %v13, %v17, %v21, 121   # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x87]
-
-	vsrd	%v0, %v0, %v0, 0
-	vsrd	%v0, %v0, %v0, 255
-	vsrd	%v0, %v0, %v31, 0
-	vsrd	%v0, %v31, %v0, 0
-	vsrd	%v31, %v0, %v0, 0
-	vsrd 	%v13, %v17, %v21, 0x79
-
-#CHECK: vstbr   %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x0e]
-#CHECK: vstbr   %v0, 0, 15              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x0e]
-#CHECK: vstbr   %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x0e]
-#CHECK: vstbr   %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x0e]
-#CHECK: vstbr   %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x0e]
-#CHECK: vstbr   %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x0e]
-#CHECK: vstbr   %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0e]
-#CHECK: vstbr   %v18, 1383(%r3,%r4), 11 # encoding: [0xe6,0x23,0x45,0x67,0xb8,0x0e]
-
-	vstbr	%v0, 0, 0
-	vstbr	%v0, 0, 15
-	vstbr	%v0, 4095, 0
-	vstbr	%v0, 0(%r15), 0
-	vstbr	%v0, 0(%r15,%r1), 0
-	vstbr	%v15, 0, 0
-	vstbr	%v31, 0, 0
-	vstbr	%v18, 0x567(%r3,%r4), 11
-
-#CHECK: vstbrf  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x20,0x0e]
-#CHECK: vstbrf  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x20,0x0e]
-#CHECK: vstbrf  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x0e]
-#CHECK: vstbrf  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x20,0x0e]
-#CHECK: vstbrf  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x0e]
-#CHECK: vstbrf  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x0e]
-#CHECK: vstbrf  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x28,0x0e]
-
-	vstbrf	%v0, 0
-	vstbrf	%v0, 4095
-	vstbrf	%v0, 0(%r15)
-	vstbrf	%v0, 0(%r15,%r1)
-	vstbrf	%v15, 0
-	vstbrf	%v31, 0
-	vstbrf	%v18, 0x567(%r3,%r4)
-
-#CHECK: vstbrg  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x30,0x0e]
-#CHECK: vstbrg  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x0e]
-#CHECK: vstbrg  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x0e]
-#CHECK: vstbrg  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x0e]
-#CHECK: vstbrg  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x0e]
-#CHECK: vstbrg  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x0e]
-#CHECK: vstbrg  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x38,0x0e]
-
-	vstbrg	%v0, 0
-	vstbrg	%v0, 4095
-	vstbrg	%v0, 0(%r15)
-	vstbrg	%v0, 0(%r15,%r1)
-	vstbrg	%v15, 0
-	vstbrg	%v31, 0
-	vstbrg	%v18, 0x567(%r3,%r4)
-
-#CHECK: vstbrh  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x10,0x0e]
-#CHECK: vstbrh  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x10,0x0e]
-#CHECK: vstbrh  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x10,0x0e]
-#CHECK: vstbrh  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x10,0x0e]
-#CHECK: vstbrh  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x10,0x0e]
-#CHECK: vstbrh  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x18,0x0e]
-#CHECK: vstbrh  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x18,0x0e]
-
-	vstbrh	%v0, 0
-	vstbrh	%v0, 4095
-	vstbrh	%v0, 0(%r15)
-	vstbrh	%v0, 0(%r15,%r1)
-	vstbrh	%v15, 0
-	vstbrh	%v31, 0
-	vstbrh	%v18, 0x567(%r3,%r4)
-
-#CHECK: vstbrq  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x40,0x0e]
-#CHECK: vstbrq  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x40,0x0e]
-#CHECK: vstbrq  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x40,0x0e]
-#CHECK: vstbrq  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x40,0x0e]
-#CHECK: vstbrq  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x40,0x0e]
-#CHECK: vstbrq  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x48,0x0e]
-#CHECK: vstbrq  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x48,0x0e]
-
-	vstbrq	%v0, 0
-	vstbrq	%v0, 4095
-	vstbrq	%v0, 0(%r15)
-	vstbrq	%v0, 0(%r15,%r1)
-	vstbrq	%v15, 0
-	vstbrq	%v31, 0
-	vstbrq	%v18, 0x567(%r3,%r4)
-
-#CHECK: vstebrf  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x0b]
-#CHECK: vstebrf  %v0, 0, 3               # encoding: [0xe6,0x00,0x00,0x00,0x30,0x0b]
-#CHECK: vstebrf  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x0b]
-#CHECK: vstebrf  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x0b]
-#CHECK: vstebrf  %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x0b]
-#CHECK: vstebrf  %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x0b]
-#CHECK: vstebrf  %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0b]
-#CHECK: vstebrf  %v18, 1383(%r3,%r4), 2  # encoding: [0xe6,0x23,0x45,0x67,0x28,0x0b]
-
-	vstebrf	%v0, 0, 0
-	vstebrf	%v0, 0, 3
-	vstebrf	%v0, 4095, 0
-	vstebrf	%v0, 0(%r15), 0
-	vstebrf	%v0, 0(%r15,%r1), 0
-	vstebrf	%v15, 0, 0
-	vstebrf	%v31, 0, 0
-	vstebrf	%v18, 1383(%r3,%r4), 2
-
-#CHECK: vstebrg  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x0a]
-#CHECK: vstebrg  %v0, 0, 1               # encoding: [0xe6,0x00,0x00,0x00,0x10,0x0a]
-#CHECK: vstebrg  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x0a]
-#CHECK: vstebrg  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x0a]
-#CHECK: vstebrg  %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x0a]
-#CHECK: vstebrg  %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x0a]
-#CHECK: vstebrg  %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0a]
-#CHECK: vstebrg  %v18, 1383(%r3,%r4), 1  # encoding: [0xe6,0x23,0x45,0x67,0x18,0x0a]
-
-	vstebrg	%v0, 0, 0
-	vstebrg	%v0, 0, 1
-	vstebrg	%v0, 4095, 0
-	vstebrg	%v0, 0(%r15), 0
-	vstebrg	%v0, 0(%r15,%r1), 0
-	vstebrg	%v15, 0, 0
-	vstebrg	%v31, 0, 0
-	vstebrg	%v18, 1383(%r3,%r4), 1
-
-#CHECK: vstebrh  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x09]
-#CHECK: vstebrh  %v0, 0, 7               # encoding: [0xe6,0x00,0x00,0x00,0x70,0x09]
-#CHECK: vstebrh  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x09]
-#CHECK: vstebrh  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x09]
-#CHECK: vstebrh  %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x09]
-#CHECK: vstebrh  %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x09]
-#CHECK: vstebrh  %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x09]
-#CHECK: vstebrh  %v18, 1383(%r3,%r4), 4  # encoding: [0xe6,0x23,0x45,0x67,0x48,0x09]
-
-	vstebrh	%v0, 0, 0
-	vstebrh	%v0, 0, 7
-	vstebrh	%v0, 4095, 0
-	vstebrh	%v0, 0(%r15), 0
-	vstebrh	%v0, 0(%r15,%r1), 0
-	vstebrh	%v15, 0, 0
-	vstebrh	%v31, 0, 0
-	vstebrh	%v18, 1383(%r3,%r4), 4
-
-#CHECK: vster   %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x0f]
-#CHECK: vster   %v0, 0, 15              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x0f]
-#CHECK: vster   %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x0f]
-#CHECK: vster   %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x0f]
-#CHECK: vster   %v0, 0(%r15,%r1), 0     # encoding: [0xe6,0x0f,0x10,0x00,0x00,0x0f]
-#CHECK: vster   %v15, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x0f]
-#CHECK: vster   %v31, 0, 0              # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x0f]
-#CHECK: vster   %v18, 1383(%r3,%r4), 11 # encoding: [0xe6,0x23,0x45,0x67,0xb8,0x0f]
-
-	vster	%v0, 0, 0
-	vster	%v0, 0, 15
-	vster	%v0, 4095, 0
-	vster	%v0, 0(%r15), 0
-	vster	%v0, 0(%r15,%r1), 0
-	vster	%v15, 0, 0
-	vster	%v31, 0, 0
-	vster	%v18, 0x567(%r3,%r4), 11
-
-#CHECK: vsterf  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x20,0x0f]
-#CHECK: vsterf  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x20,0x0f]
-#CHECK: vsterf  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x20,0x0f]
-#CHECK: vsterf  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x20,0x0f]
-#CHECK: vsterf  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x20,0x0f]
-#CHECK: vsterf  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x28,0x0f]
-#CHECK: vsterf  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x28,0x0f]
-
-	vsterf	%v0, 0
-	vsterf	%v0, 4095
-	vsterf	%v0, 0(%r15)
-	vsterf	%v0, 0(%r15,%r1)
-	vsterf	%v15, 0
-	vsterf	%v31, 0
-	vsterf	%v18, 0x567(%r3,%r4)
-
-#CHECK: vsterg  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x30,0x0f]
-#CHECK: vsterg  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x0f]
-#CHECK: vsterg  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x0f]
-#CHECK: vsterg  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x0f]
-#CHECK: vsterg  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x0f]
-#CHECK: vsterg  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x0f]
-#CHECK: vsterg  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x38,0x0f]
-
-	vsterg	%v0, 0
-	vsterg	%v0, 4095
-	vsterg	%v0, 0(%r15)
-	vsterg	%v0, 0(%r15,%r1)
-	vsterg	%v15, 0
-	vsterg	%v31, 0
-	vsterg	%v18, 0x567(%r3,%r4)
-
-#CHECK: vsterh  %v0, 0                  # encoding: [0xe6,0x00,0x00,0x00,0x10,0x0f]
-#CHECK: vsterh  %v0, 4095               # encoding: [0xe6,0x00,0x0f,0xff,0x10,0x0f]
-#CHECK: vsterh  %v0, 0(%r15)            # encoding: [0xe6,0x00,0xf0,0x00,0x10,0x0f]
-#CHECK: vsterh  %v0, 0(%r15,%r1)        # encoding: [0xe6,0x0f,0x10,0x00,0x10,0x0f]
-#CHECK: vsterh  %v15, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x10,0x0f]
-#CHECK: vsterh  %v31, 0                 # encoding: [0xe6,0xf0,0x00,0x00,0x18,0x0f]
-#CHECK: vsterh  %v18, 1383(%r3,%r4)     # encoding: [0xe6,0x23,0x45,0x67,0x18,0x0f]
-
-	vsterh	%v0, 0
-	vsterh	%v0, 4095
-	vsterh	%v0, 0(%r15)
-	vsterh	%v0, 0(%r15,%r1)
-	vsterh	%v15, 0
-	vsterh	%v31, 0
-	vsterh	%v18, 0x567(%r3,%r4)
-
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 0, 0    # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8b]
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 15, 0   # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x8b]
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 0, 0    # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8b]
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 15, 0   # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x8b]
-#CHECK: vstrs    %v0, %v0, %v0, %v0, 0, 12   # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x8b]
-#CHECK: vstrs    %v0, %v0, %v0, %v15, 0, 0   # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x8b]
-#CHECK: vstrs    %v0, %v0, %v0, %v31, 0, 0   # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8b]
-#CHECK: vstrs    %v0, %v0, %v15, %v0, 0, 0   # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x8b]
-#CHECK: vstrs    %v0, %v0, %v31, %v0, 0, 0   # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8b]
-#CHECK: vstrs    %v0, %v15, %v0, %v0, 0, 0   # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x8b]
-#CHECK: vstrs    %v0, %v31, %v0, %v0, 0, 0   # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8b]
-#CHECK: vstrs    %v15, %v0, %v0, %v0, 0, 0   # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x8b]
-#CHECK: vstrs    %v31, %v0, %v0, %v0, 0, 0   # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8b]
-#CHECK: vstrs    %v18, %v3, %v20, %v5, 11, 4 # encoding: [0xe7,0x23,0x4b,0x40,0x5a,0x8b]
-#CHECK: vstrs    %v18, %v3, %v20, %v5, 0, 15 # encoding: [0xe7,0x23,0x40,0xf0,0x5a,0x8b]
-
-        vstrs    %v0, %v0, %v0, %v0, 0
-        vstrs    %v0, %v0, %v0, %v0, 15
-        vstrs    %v0, %v0, %v0, %v0, 0, 0
-        vstrs    %v0, %v0, %v0, %v0, 15, 0
-        vstrs    %v0, %v0, %v0, %v0, 0, 12
-        vstrs    %v0, %v0, %v0, %v15, 0
-        vstrs    %v0, %v0, %v0, %v31, 0
-        vstrs    %v0, %v0, %v15, %v0, 0
-        vstrs    %v0, %v0, %v31, %v0, 0
-        vstrs    %v0, %v15, %v0, %v0, 0
-        vstrs    %v0, %v31, %v0, %v0, 0
-        vstrs    %v15, %v0, %v0, %v0, 0
-        vstrs    %v31, %v0, %v0, %v0, 0
-        vstrs    %v18, %v3, %v20, %v5, 11, 4
-        vstrs    %v18, %v3, %v20, %v5, 0, 15
-
-#CHECK: vstrsb   %v0, %v0, %v0, %v0, 0       # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8b]
-#CHECK: vstrsb   %v0, %v0, %v0, %v0, 0       # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8b]
-#CHECK: vstrsb   %v0, %v0, %v0, %v0, 12      # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x8b]
-#CHECK: vstrsb   %v0, %v0, %v0, %v15, 0      # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x8b]
-#CHECK: vstrsb   %v0, %v0, %v0, %v31, 0      # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x8b]
-#CHECK: vstrsb   %v0, %v0, %v15, %v0, 0      # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x8b]
-#CHECK: vstrsb   %v0, %v0, %v31, %v0, 0      # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x8b]
-#CHECK: vstrsb   %v0, %v15, %v0, %v0, 0      # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x8b]
-#CHECK: vstrsb   %v0, %v31, %v0, %v0, 0      # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x8b]
-#CHECK: vstrsb   %v15, %v0, %v0, %v0, 0      # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x8b]
-#CHECK: vstrsb   %v31, %v0, %v0, %v0, 0      # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x8b]
-#CHECK: vstrsb   %v18, %v3, %v20, %v5, 4     # encoding: [0xe7,0x23,0x40,0x40,0x5a,0x8b]
-#CHECK: vstrsb   %v18, %v3, %v20, %v5, 15    # encoding: [0xe7,0x23,0x40,0xf0,0x5a,0x8b]
-#CHECK: vstrszb  %v18, %v3, %v20, %v5        # encoding: [0xe7,0x23,0x40,0x20,0x5a,0x8b]
-
-        vstrsb   %v0, %v0, %v0, %v0
-        vstrsb   %v0, %v0, %v0, %v0, 0
-        vstrsb   %v0, %v0, %v0, %v0, 12
-        vstrsb   %v0, %v0, %v0, %v15
-        vstrsb   %v0, %v0, %v0, %v31
-        vstrsb   %v0, %v0, %v15, %v0
-        vstrsb   %v0, %v0, %v31, %v0
-        vstrsb   %v0, %v15, %v0, %v0
-        vstrsb   %v0, %v31, %v0, %v0
-        vstrsb   %v15, %v0, %v0, %v0
-        vstrsb   %v31, %v0, %v0, %v0
-        vstrsb   %v18, %v3, %v20, %v5, 4
-        vstrsb   %v18, %v3, %v20, %v5, 15
-        vstrszb  %v18, %v3, %v20, %v5
-
-#CHECK: vstrsf   %v0, %v0, %v0, %v0, 0       # encoding: [0xe7,0x00,0x02,0x00,0x00,0x8b]
-#CHECK: vstrsf   %v0, %v0, %v0, %v0, 0       # encoding: [0xe7,0x00,0x02,0x00,0x00,0x8b]
-#CHECK: vstrsf   %v0, %v0, %v0, %v0, 12      # encoding: [0xe7,0x00,0x02,0xc0,0x00,0x8b]
-#CHECK: vstrsf   %v0, %v0, %v0, %v15, 0      # encoding: [0xe7,0x00,0x02,0x00,0xf0,0x8b]
-#CHECK: vstrsf   %v0, %v0, %v0, %v31, 0      # encoding: [0xe7,0x00,0x02,0x00,0xf1,0x8b]
-#CHECK: vstrsf   %v0, %v0, %v15, %v0, 0      # encoding: [0xe7,0x00,0xf2,0x00,0x00,0x8b]
-#CHECK: vstrsf   %v0, %v0, %v31, %v0, 0      # encoding: [0xe7,0x00,0xf2,0x00,0x02,0x8b]
-#CHECK: vstrsf   %v0, %v15, %v0, %v0, 0      # encoding: [0xe7,0x0f,0x02,0x00,0x00,0x8b]
-#CHECK: vstrsf   %v0, %v31, %v0, %v0, 0      # encoding: [0xe7,0x0f,0x02,0x00,0x04,0x8b]
-#CHECK: vstrsf   %v15, %v0, %v0, %v0, 0      # encoding: [0xe7,0xf0,0x02,0x00,0x00,0x8b]
-#CHECK: vstrsf   %v31, %v0, %v0, %v0, 0      # encoding: [0xe7,0xf0,0x02,0x00,0x08,0x8b]
-#CHECK: vstrsf   %v18, %v3, %v20, %v5, 4     # encoding: [0xe7,0x23,0x42,0x40,0x5a,0x8b]
-#CHECK: vstrsf   %v18, %v3, %v20, %v5, 15    # encoding: [0xe7,0x23,0x42,0xf0,0x5a,0x8b]
-#CHECK: vstrszf  %v18, %v3, %v20, %v5        # encoding: [0xe7,0x23,0x42,0x20,0x5a,0x8b]
-
-        vstrsf   %v0, %v0, %v0, %v0
-        vstrsf   %v0, %v0, %v0, %v0, 0
-        vstrsf   %v0, %v0, %v0, %v0, 12
-        vstrsf   %v0, %v0, %v0, %v15
-        vstrsf   %v0, %v0, %v0, %v31
-        vstrsf   %v0, %v0, %v15, %v0
-        vstrsf   %v0, %v0, %v31, %v0
-        vstrsf   %v0, %v15, %v0, %v0
-        vstrsf   %v0, %v31, %v0, %v0
-        vstrsf   %v15, %v0, %v0, %v0
-        vstrsf   %v31, %v0, %v0, %v0
-        vstrsf   %v18, %v3, %v20, %v5, 4
-        vstrsf   %v18, %v3, %v20, %v5, 15
-        vstrszf  %v18, %v3, %v20, %v5
-
-#CHECK: vstrsh   %v0, %v0, %v0, %v0, 0       # encoding: [0xe7,0x00,0x01,0x00,0x00,0x8b]
-#CHECK: vstrsh   %v0, %v0, %v0, %v0, 0       # encoding: [0xe7,0x00,0x01,0x00,0x00,0x8b]
-#CHECK: vstrsh   %v0, %v0, %v0, %v0, 12      # encoding: [0xe7,0x00,0x01,0xc0,0x00,0x8b]
-#CHECK: vstrsh   %v0, %v0, %v0, %v15, 0      # encoding: [0xe7,0x00,0x01,0x00,0xf0,0x8b]
-#CHECK: vstrsh   %v0, %v0, %v0, %v31, 0      # encoding: [0xe7,0x00,0x01,0x00,0xf1,0x8b]
-#CHECK: vstrsh   %v0, %v0, %v15, %v0, 0      # encoding: [0xe7,0x00,0xf1,0x00,0x00,0x8b]
-#CHECK: vstrsh   %v0, %v0, %v31, %v0, 0      # encoding: [0xe7,0x00,0xf1,0x00,0x02,0x8b]
-#CHECK: vstrsh   %v0, %v15, %v0, %v0, 0      # encoding: [0xe7,0x0f,0x01,0x00,0x00,0x8b]
-#CHECK: vstrsh   %v0, %v31, %v0, %v0, 0      # encoding: [0xe7,0x0f,0x01,0x00,0x04,0x8b]
-#CHECK: vstrsh   %v15, %v0, %v0, %v0, 0      # encoding: [0xe7,0xf0,0x01,0x00,0x00,0x8b]
-#CHECK: vstrsh   %v31, %v0, %v0, %v0, 0      # encoding: [0xe7,0xf0,0x01,0x00,0x08,0x8b]
-#CHECK: vstrsh   %v18, %v3, %v20, %v5, 4     # encoding: [0xe7,0x23,0x41,0x40,0x5a,0x8b]
-#CHECK: vstrsh   %v18, %v3, %v20, %v5, 15    # encoding: [0xe7,0x23,0x41,0xf0,0x5a,0x8b]
-#CHECK: vstrszh  %v18, %v3, %v20, %v5        # encoding: [0xe7,0x23,0x41,0x20,0x5a,0x8b]
-
-        vstrsh   %v0, %v0, %v0, %v0
-        vstrsh   %v0, %v0, %v0, %v0, 0
-        vstrsh   %v0, %v0, %v0, %v0, 12
-        vstrsh   %v0, %v0, %v0, %v15
-        vstrsh   %v0, %v0, %v0, %v31
-        vstrsh   %v0, %v0, %v15, %v0
-        vstrsh   %v0, %v0, %v31, %v0
-        vstrsh   %v0, %v15, %v0, %v0
-        vstrsh   %v0, %v31, %v0, %v0
-        vstrsh   %v15, %v0, %v0, %v0
-        vstrsh   %v31, %v0, %v0, %v0
-        vstrsh   %v18, %v3, %v20, %v5, 4
-        vstrsh   %v18, %v3, %v20, %v5, 15
-        vstrszh  %v18, %v3, %v20, %v5
-
-#CHECK: wcefb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc3]
-#CHECK: wcefb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc3]
-#CHECK: wcefb   %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x20,0xc3]
-#CHECK: wcefb   %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc3]
-#CHECK: wcefb   %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc3]
-#CHECK: wcefb   %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x24,0xc3]
-#CHECK: wcefb   %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x28,0xc3]
-#CHECK: wcefb   %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x24,0xc3]
-
-	wcefb	%v0, %v0, 0, 0
-	wcefb   %f0, %f0, 0, 0
- 	wcefb	%v0, %v0, 0, 15
-	wcefb	%v0, %v0, 4, 0
-	wcefb	%v0, %v0, 12, 0
-	wcefb	%v0, %v31, 0, 0
-	wcefb	%v31, %v0, 0, 0
-	wcefb	%v14, %v17, 4, 10
-
-#CHECK: wcelfb  %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc1]
-#CHECK: wcelfb  %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc1]
-#CHECK: wcelfb  %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x20,0xc1]
-#CHECK: wcelfb  %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc1]
-#CHECK: wcelfb  %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc1]
-#CHECK: wcelfb  %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x24,0xc1]
-#CHECK: wcelfb  %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x28,0xc1]
-#CHECK: wcelfb  %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x24,0xc1]
-
-	wcelfb	%v0, %v0, 0, 0
-	wcelfb  %f0, %f0, 0, 0
- 	wcelfb	%v0, %v0, 0, 15
-	wcelfb	%v0, %v0, 4, 0
-	wcelfb	%v0, %v0, 12, 0
-	wcelfb	%v0, %v31, 0, 0
-	wcelfb	%v31, %v0, 0, 0
-	wcelfb	%v14, %v17, 4, 10
-
-#CHECK: wcfeb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc2]
-#CHECK: wcfeb   %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc2]
-#CHECK: wcfeb   %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x20,0xc2]
-#CHECK: wcfeb   %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc2]
-#CHECK: wcfeb   %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc2]
-#CHECK: wcfeb   %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x24,0xc2]
-#CHECK: wcfeb   %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x28,0xc2]
-#CHECK: wcfeb   %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x24,0xc2]
-
-	wcfeb	%v0, %v0, 0, 0
-	wcfeb  	%f0, %f0, 0, 0
- 	wcfeb	%v0, %v0, 0, 15
-	wcfeb	%v0, %v0, 4, 0
-	wcfeb	%v0, %v0, 12, 0
-	wcfeb	%v0, %v31, 0, 0
-	wcfeb	%v31, %v0, 0, 0
-	wcfeb	%v14, %v17, 4, 10
-
-#CHECK: wclfeb  %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc0]
-#CHECK: wclfeb  %f0, %f0, 0, 0          # encoding: [0xe7,0x00,0x00,0x08,0x20,0xc0]
-#CHECK: wclfeb  %f0, %f0, 0, 15         # encoding: [0xe7,0x00,0x00,0xf8,0x20,0xc0]
-#CHECK: wclfeb  %f0, %f0, 4, 0          # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc0]
-#CHECK: wclfeb  %f0, %f0, 12, 0         # encoding: [0xe7,0x00,0x00,0x0c,0x20,0xc0]
-#CHECK: wclfeb  %f0, %v31, 0, 0         # encoding: [0xe7,0x0f,0x00,0x08,0x24,0xc0]
-#CHECK: wclfeb  %v31, %f0, 0, 0         # encoding: [0xe7,0xf0,0x00,0x08,0x28,0xc0]
-#CHECK: wclfeb  %f14, %v17, 4, 10       # encoding: [0xe7,0xe1,0x00,0xac,0x24,0xc0]
-
-	wclfeb	%v0, %v0, 0, 0
-	wclfeb  %f0, %f0, 0, 0
- 	wclfeb	%v0, %v0, 0, 15
-	wclfeb	%v0, %v0, 4, 0
-	wclfeb	%v0, %v0, 12, 0
-	wclfeb	%v0, %v31, 0, 0
-	wclfeb	%v31, %v0, 0, 0
-	wclfeb	%v14, %v17, 4, 10
-

Copied: llvm/trunk/test/MC/SystemZ/insn-good-z15.s (from r372434, llvm/trunk/test/MC/SystemZ/insn-good-arch13.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z15.s?p2=llvm/trunk/test/MC/SystemZ/insn-good-z15.s&p1=llvm/trunk/test/MC/SystemZ/insn-good-arch13.s&r1=372434&r2=372435&rev=372435&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-arch13.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z15.s Fri Sep 20 16:04:45 2019
@@ -1,4 +1,6 @@
-# For arch13 and above.
+# For z15 and above.
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z15 -show-encoding %s \
+# RUN:   | FileCheck %s
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch13 -show-encoding %s \
 # RUN:   | FileCheck %s
 


