[PATCH] D67640: [RISCV] Fix static analysis issues
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 20 06:46:25 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL372391: [RISCV] Fix static analysis issues (authored by luismarques, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D67640?vs=220402&id=221020#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67640/new/
https://reviews.llvm.org/D67640
Files:
llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
Index: llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -374,8 +374,8 @@
return true;
// Given only Imm, ensuring that the actually specified constant is either
// a signed or unsigned 64-bit number is unfortunately impossible.
- bool IsInRange = isRV64() ? true : isInt<32>(Imm) || isUInt<32>(Imm);
- return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None;
+ return IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None &&
+ (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm)));
}
bool isUImmLog2XLen() const {
Index: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1903,8 +1903,7 @@
// ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
// offsets to even-numbered registered remain 2*XLEN-aligned.
if (Idx % 2) {
- FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes,
- true);
+ MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true);
VarArgsSaveSize += XLenInBytes;
}
Index: llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -68,7 +68,7 @@
RISCVMatInt::InstSeq Seq;
RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq);
- SDNode *Result;
+ SDNode *Result = nullptr;
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
for (RISCVMatInt::Inst &Inst : Seq) {
SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
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