[PATCH] D67717: [DebugInfo] Exclude memory location values as parameter entry values

[Nikola Prica via Phabricator via llvm-commits]

NikolaPrica updated this revision to Diff 221024.
NikolaPrica added a comment.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

-Update lldb test.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67717/new/

https://reviews.llvm.org/D67717

Files:
  lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/main.cpp
  llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir


Index: llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
===================================================================
--- llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
+++ llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
@@ -21,10 +21,8 @@
 # CHECK-NEXT:     DW_AT_low_pc
 # CHECK-EMPTY:
 # CHECK-NEXT:     DW_TAG_GNU_call_site_parameter
-# CHECK-NEXT:       DW_AT_location      (DW_OP_reg2 RCX)
-# CHECK-NEXT:       DW_AT_GNU_call_site_value   (DW_OP_fbreg +8, DW_OP_deref)
-# CHECK-EMPTY:
-# CHECK-NEXT:     DW_TAG_GNU_call_site_parameter
+# RCX loads memory location. We can't rely that memory location won't be changed.
+# CHECK-NOT:       DW_AT_location      (DW_OP_reg2 RCX)
 # CHECK-NEXT:       DW_AT_location      (DW_OP_reg4 RSI)
 # CHECK-NEXT:       DW_AT_GNU_call_site_value   (DW_OP_lit4)
 # CHECK-EMPTY:
Index: llvm/lib/CodeGen/TargetInstrInfo.cpp
===================================================================
--- llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1133,18 +1133,6 @@
   } else if (MI.isMoveImmediate()) {
     Op = &MI.getOperand(1);
     return ParamLoadedValue(*Op, Expr);
-  } else if (MI.hasOneMemOperand()) {
-    int64_t Offset;
-    const auto &TRI = MF->getSubtarget().getRegisterInfo();
-    const auto &TII = MF->getSubtarget().getInstrInfo();
-    const MachineOperand *BaseOp;
-
-    if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
-      return None;
-
-    Expr = DIExpression::prepend(Expr, DIExpression::DerefAfter, Offset);
-    Op = BaseOp;
-    return ParamLoadedValue(*Op, Expr);
   }
 
   return None;
Index: llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
===================================================================
--- llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -246,8 +246,8 @@
   // a call site parameter expression and if that expression is just a register
   // location, emit it with addBReg and offset 0, because we should emit a DWARF
   // expression representing a value, rather than a location.
-  if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() ||
-                                                       isEntryValue())) {
+  if (!isMemoryLocation() && !HasComplexExpression &&
+      (!isParameterValue() || isEntryValue())) {
     for (auto &Reg : DwarfRegs) {
       if (Reg.DwarfRegNo >= 0)
         addReg(Reg.DwarfRegNo, Reg.Comment);
@@ -413,6 +413,9 @@
       break;
     case dwarf::DW_OP_deref:
       assert(!isRegisterLocation());
+      // For more detailed explanation see llvm.org/PR43343.
+      assert(!isParameterValue() && "Parameter entry values should not be "
+                                    "dereferenced due to safety reasons.");
       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
         // Turning this into a memory location description makes the deref
         // implicit.
Index: lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/main.cpp
===================================================================
--- lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/main.cpp
+++ lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/main.cpp
@@ -152,7 +152,10 @@
   func2(sink, 123);
 
   // Test evaluation of "DW_OP_fbreg -24, DW_OP_deref" in the parent frame.
+  // Disabled for now, see: llvm.org/PR43343
+#if 0
   func3(sink, s1.field2);
+#endif
 
   // The sequences `main -> func4 -> func{5,6}_amb -> sink` are both plausible.
   // Test that lldb doesn't attempt to guess which one occurred: entry value


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