[www-releases] r372328 - Check in 9.0.0 source and docs
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 19 07:32:55 PDT 2019
Added: www-releases/trunk/9.0.0/docs/YamlIO.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/9.0.0/docs/YamlIO.html?rev=372328&view=auto
==============================================================================
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+ <div class="section" id="yaml-i-o">
+<h1>YAML I/O<a class="headerlink" href="#yaml-i-o" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction-to-yaml" id="id1">Introduction to YAML</a></li>
+<li><a class="reference internal" href="#introduction-to-yaml-i-o" id="id2">Introduction to YAML I/O</a></li>
+<li><a class="reference internal" href="#error-handling" id="id3">Error Handling</a></li>
+<li><a class="reference internal" href="#scalars" id="id4">Scalars</a><ul>
+<li><a class="reference internal" href="#built-in-types" id="id5">Built-in types</a></li>
+<li><a class="reference internal" href="#unique-types" id="id6">Unique types</a></li>
+<li><a class="reference internal" href="#hex-types" id="id7">Hex types</a></li>
+<li><a class="reference internal" href="#scalarenumerationtraits" id="id8">ScalarEnumerationTraits</a></li>
+<li><a class="reference internal" href="#bitvalue" id="id9">BitValue</a></li>
+<li><a class="reference internal" href="#custom-scalar" id="id10">Custom Scalar</a></li>
+<li><a class="reference internal" href="#block-scalars" id="id11">Block Scalars</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#mappings" id="id12">Mappings</a><ul>
+<li><a class="reference internal" href="#no-normalization" id="id13">No Normalization</a></li>
+<li><a class="reference internal" href="#normalization" id="id14">Normalization</a></li>
+<li><a class="reference internal" href="#default-values" id="id15">Default values</a></li>
+<li><a class="reference internal" href="#order-of-keys" id="id16">Order of Keys</a></li>
+<li><a class="reference internal" href="#tags" id="id17">Tags</a></li>
+<li><a class="reference internal" href="#validation" id="id18">Validation</a></li>
+<li><a class="reference internal" href="#flow-mapping" id="id19">Flow Mapping</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#sequence" id="id20">Sequence</a><ul>
+<li><a class="reference internal" href="#flow-sequence" id="id21">Flow Sequence</a></li>
+<li><a class="reference internal" href="#utility-macros" id="id22">Utility Macros</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#document-list" id="id23">Document List</a></li>
+<li><a class="reference internal" href="#user-context-data" id="id24">User Context Data</a></li>
+<li><a class="reference internal" href="#output" id="id25">Output</a></li>
+<li><a class="reference internal" href="#input" id="id26">Input</a></li>
+</ul>
+</div>
+<div class="section" id="introduction-to-yaml">
+<h2><a class="toc-backref" href="#id1">Introduction to YAML</a><a class="headerlink" href="#introduction-to-yaml" title="Permalink to this headline">¶</a></h2>
+<p>YAML is a human readable data serialization language. The full YAML language
+spec can be read at <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html#Introduction">yaml.org</a>. The simplest form of
+yaml is just âscalarsâ, âmappingsâ, and âsequencesâ. A scalar is any number
+or string. The pound/hash symbol (#) begins a comment line. A mapping is
+a set of key-value pairs where the key ends with a colon. For example:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="c1"># a mapping</span>
+<span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+<span class="nt">hat-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">7</span>
+</pre></div>
+</div>
+<p>A sequence is a list of items where each item starts with a leading dash (â-â).
+For example:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="c1"># a sequence</span>
+<span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">x86</span>
+<span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">x86_64</span>
+<span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">PowerPC</span>
+</pre></div>
+</div>
+<p>You can combine mappings and sequences by indenting. For example a sequence
+of mappings in which one of the mapping values is itself a sequence:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="c1"># a sequence of mappings with one key's value being a sequence</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+ <span class="nt">cpus</span><span class="p">:</span>
+ <span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">x86</span>
+ <span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">x86_64</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Bob</span>
+ <span class="nt">cpus</span><span class="p">:</span>
+ <span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">x86</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Dan</span>
+ <span class="nt">cpus</span><span class="p">:</span>
+ <span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">PowerPC</span>
+ <span class="p p-Indicator">-</span> <span class="l l-Scalar l-Scalar-Plain">x86</span>
+</pre></div>
+</div>
+<p>Sometime sequences are known to be short and the one entry per line is too
+verbose, so YAML offers an alternate syntax for sequences called a âFlow
+Sequenceâ in which you put comma separated sequence elements into square
+brackets. The above example could then be simplified to :</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="c1"># a sequence of mappings with one key's value being a flow sequence</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+ <span class="nt">cpus</span><span class="p">:</span> <span class="p p-Indicator">[</span> <span class="nv">x86</span><span class="p p-Indicator">,</span> <span class="nv">x86_64</span> <span class="p p-Indicator">]</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Bob</span>
+ <span class="nt">cpus</span><span class="p">:</span> <span class="p p-Indicator">[</span> <span class="nv">x86</span> <span class="p p-Indicator">]</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Dan</span>
+ <span class="nt">cpus</span><span class="p">:</span> <span class="p p-Indicator">[</span> <span class="nv">PowerPC</span><span class="p p-Indicator">,</span> <span class="nv">x86</span> <span class="p p-Indicator">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="introduction-to-yaml-i-o">
+<h2><a class="toc-backref" href="#id2">Introduction to YAML I/O</a><a class="headerlink" href="#introduction-to-yaml-i-o" title="Permalink to this headline">¶</a></h2>
+<p>The use of indenting makes the YAML easy for a human to read and understand,
+but having a program read and write YAML involves a lot of tedious details.
+The YAML I/O library structures and simplifies reading and writing YAML
+documents.</p>
+<p>YAML I/O assumes you have some ânativeâ data structures which you want to be
+able to dump as YAML and recreate from YAML. The first step is to try
+writing example YAML for your data structures. You may find after looking at
+possible YAML representations that a direct mapping of your data structures
+to YAML is not very readable. Often the fields are not in the order that
+a human would find readable. Or the same information is replicated in multiple
+locations, making it hard for a human to write such YAML correctly.</p>
+<p>In relational database theory there is a design step called normalization in
+which you reorganize fields and tables. The same considerations need to
+go into the design of your YAML encoding. But, you may not want to change
+your existing native data structures. Therefore, when writing out YAML
+there may be a normalization step, and when reading YAML there would be a
+corresponding denormalization step.</p>
+<p>YAML I/O uses a non-invasive, traits based design. YAML I/O defines some
+abstract base templates. You specialize those templates on your data types.
+For instance, if you have an enumerated type FooBar you could specialize
+ScalarEnumerationTraits on that type and define the enumeration() method:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">ScalarEnumerationTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">ScalarEnumerationTraits</span><span class="o"><</span><span class="n">FooBar</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">enumeration</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">FooBar</span> <span class="o">&</span><span class="n">value</span><span class="p">)</span> <span class="p">{</span>
+ <span class="p">...</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>As with all YAML I/O template specializations, the ScalarEnumerationTraits is used for
+both reading and writing YAML. That is, the mapping between in-memory enum
+values and the YAML string representation is only in one place.
+This assures that the code for writing and parsing of YAML stays in sync.</p>
+<p>To specify a YAML mappings, you define a specialization on
+llvm::yaml::MappingTraits.
+If your native data structure happens to be a struct that is already normalized,
+then the specialization is simple. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Person</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Person</span> <span class="o">&</span><span class="n">info</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"name"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">name</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapOptional</span><span class="p">(</span><span class="s">"hat-size"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">hatSize</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>A YAML sequence is automatically inferred if you data type has begin()/end()
+iterators and a push_back() method. Therefore any of the STL containers
+(such as std::vector<>) will automatically translate to YAML sequences.</p>
+<p>Once you have defined specializations for your data types, you can
+programmatically use YAML I/O to write a YAML document:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">Output</span><span class="p">;</span>
+
+<span class="n">Person</span> <span class="n">tom</span><span class="p">;</span>
+<span class="n">tom</span><span class="p">.</span><span class="n">name</span> <span class="o">=</span> <span class="s">"Tom"</span><span class="p">;</span>
+<span class="n">tom</span><span class="p">.</span><span class="n">hatSize</span> <span class="o">=</span> <span class="mi">8</span><span class="p">;</span>
+<span class="n">Person</span> <span class="n">dan</span><span class="p">;</span>
+<span class="n">dan</span><span class="p">.</span><span class="n">name</span> <span class="o">=</span> <span class="s">"Dan"</span><span class="p">;</span>
+<span class="n">dan</span><span class="p">.</span><span class="n">hatSize</span> <span class="o">=</span> <span class="mi">7</span><span class="p">;</span>
+<span class="n">std</span><span class="o">::</span><span class="n">vector</span><span class="o"><</span><span class="n">Person</span><span class="o">></span> <span class="n">persons</span><span class="p">;</span>
+<span class="n">persons</span><span class="p">.</span><span class="n">push_back</span><span class="p">(</span><span class="n">tom</span><span class="p">);</span>
+<span class="n">persons</span><span class="p">.</span><span class="n">push_back</span><span class="p">(</span><span class="n">dan</span><span class="p">);</span>
+
+<span class="n">Output</span> <span class="nf">yout</span><span class="p">(</span><span class="n">llvm</span><span class="o">::</span><span class="n">outs</span><span class="p">());</span>
+<span class="n">yout</span> <span class="o"><<</span> <span class="n">persons</span><span class="p">;</span>
+</pre></div>
+</div>
+<p>This would write the following:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+ <span class="nt">hat-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">8</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Dan</span>
+ <span class="nt">hat-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">7</span>
+</pre></div>
+</div>
+<p>And you can also read such YAML documents with the following code:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">Input</span><span class="p">;</span>
+
+<span class="k">typedef</span> <span class="n">std</span><span class="o">::</span><span class="n">vector</span><span class="o"><</span><span class="n">Person</span><span class="o">></span> <span class="n">PersonList</span><span class="p">;</span>
+<span class="n">std</span><span class="o">::</span><span class="n">vector</span><span class="o"><</span><span class="n">PersonList</span><span class="o">></span> <span class="n">docs</span><span class="p">;</span>
+
+<span class="n">Input</span> <span class="nf">yin</span><span class="p">(</span><span class="n">document</span><span class="p">.</span><span class="n">getBuffer</span><span class="p">());</span>
+<span class="n">yin</span> <span class="o">>></span> <span class="n">docs</span><span class="p">;</span>
+
+<span class="k">if</span> <span class="p">(</span> <span class="n">yin</span><span class="p">.</span><span class="n">error</span><span class="p">()</span> <span class="p">)</span>
+ <span class="k">return</span><span class="p">;</span>
+
+<span class="c1">// Process read document</span>
+<span class="k">for</span> <span class="p">(</span> <span class="n">PersonList</span> <span class="o">&</span><span class="nl">pl</span> <span class="p">:</span> <span class="n">docs</span> <span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span> <span class="n">Person</span> <span class="o">&</span><span class="nl">person</span> <span class="p">:</span> <span class="n">pl</span> <span class="p">)</span> <span class="p">{</span>
+ <span class="n">cout</span> <span class="o"><<</span> <span class="s">"name="</span> <span class="o"><<</span> <span class="n">person</span><span class="p">.</span><span class="n">name</span><span class="p">;</span>
+ <span class="p">}</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>One other feature of YAML is the ability to define multiple documents in a
+single file. That is why reading YAML produces a vector of your document type.</p>
+</div>
+<div class="section" id="error-handling">
+<h2><a class="toc-backref" href="#id3">Error Handling</a><a class="headerlink" href="#error-handling" title="Permalink to this headline">¶</a></h2>
+<p>When parsing a YAML document, if the input does not match your schema (as
+expressed in your XxxTraits<> specializations). YAML I/O
+will print out an error message and your Input objectâs error() method will
+return true. For instance the following document:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+ <span class="nt">shoe-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">12</span>
+<span class="p p-Indicator">-</span> <span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Dan</span>
+ <span class="nt">hat-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">7</span>
+</pre></div>
+</div>
+<p>Has a key (shoe-size) that is not defined in the schema. YAML I/O will
+automatically generate this error:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="l l-Scalar l-Scalar-Plain">YAML:2:2</span><span class="p p-Indicator">:</span> <span class="nt">error</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">unknown key 'shoe-size'</span>
+ <span class="l l-Scalar l-Scalar-Plain">shoe-size</span><span class="p p-Indicator">:</span> <span class="l l-Scalar l-Scalar-Plain">12</span>
+ <span class="l l-Scalar l-Scalar-Plain">^~~~~~~~~</span>
+</pre></div>
+</div>
+<p>Similar errors are produced for other input not conforming to the schema.</p>
+</div>
+<div class="section" id="scalars">
+<h2><a class="toc-backref" href="#id4">Scalars</a><a class="headerlink" href="#scalars" title="Permalink to this headline">¶</a></h2>
+<p>YAML scalars are just strings (i.e. not a sequence or mapping). The YAML I/O
+library provides support for translating between YAML scalars and specific
+C++ types.</p>
+<div class="section" id="built-in-types">
+<h3><a class="toc-backref" href="#id5">Built-in types</a><a class="headerlink" href="#built-in-types" title="Permalink to this headline">¶</a></h3>
+<p>The following types have built-in support in YAML I/O:</p>
+<ul class="simple">
+<li>bool</li>
+<li>float</li>
+<li>double</li>
+<li>StringRef</li>
+<li>std::string</li>
+<li>int64_t</li>
+<li>int32_t</li>
+<li>int16_t</li>
+<li>int8_t</li>
+<li>uint64_t</li>
+<li>uint32_t</li>
+<li>uint16_t</li>
+<li>uint8_t</li>
+</ul>
+<p>That is, you can use those types in fields of MappingTraits or as element type
+in sequence. When reading, YAML I/O will validate that the string found
+is convertible to that type and error out if not.</p>
+</div>
+<div class="section" id="unique-types">
+<h3><a class="toc-backref" href="#id6">Unique types</a><a class="headerlink" href="#unique-types" title="Permalink to this headline">¶</a></h3>
+<p>Given that YAML I/O is trait based, the selection of how to convert your data
+to YAML is based on the type of your data. But in C++ type matching, typedefs
+do not generate unique type names. That means if you have two typedefs of
+unsigned int, to YAML I/O both types look exactly like unsigned int. To
+facilitate make unique type names, YAML I/O provides a macro which is used
+like a typedef on built-in types, but expands to create a class with conversion
+operators to and from the base type. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="n">LLVM_YAML_STRONG_TYPEDEF</span><span class="p">(</span><span class="kt">uint32_t</span><span class="p">,</span> <span class="n">MyFooFlags</span><span class="p">)</span>
+<span class="n">LLVM_YAML_STRONG_TYPEDEF</span><span class="p">(</span><span class="kt">uint32_t</span><span class="p">,</span> <span class="n">MyBarFlags</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>This generates two classes MyFooFlags and MyBarFlags which you can use in your
+native data structures instead of uint32_t. They are implicitly
+converted to and from uint32_t. The point of creating these unique types
+is that you can now specify traits on them to get different YAML conversions.</p>
+</div>
+<div class="section" id="hex-types">
+<h3><a class="toc-backref" href="#id7">Hex types</a><a class="headerlink" href="#hex-types" title="Permalink to this headline">¶</a></h3>
+<p>An example use of a unique type is that YAML I/O provides fixed sized unsigned
+integers that are written with YAML I/O as hexadecimal instead of the decimal
+format used by the built-in integer types:</p>
+<ul class="simple">
+<li>Hex64</li>
+<li>Hex32</li>
+<li>Hex16</li>
+<li>Hex8</li>
+</ul>
+<p>You can use llvm::yaml::Hex32 instead of uint32_t and the only different will
+be that when YAML I/O writes out that type it will be formatted in hexadecimal.</p>
+</div>
+<div class="section" id="scalarenumerationtraits">
+<h3><a class="toc-backref" href="#id8">ScalarEnumerationTraits</a><a class="headerlink" href="#scalarenumerationtraits" title="Permalink to this headline">¶</a></h3>
+<p>YAML I/O supports translating between in-memory enumerations and a set of string
+values in YAML documents. This is done by specializing ScalarEnumerationTraits<>
+on your enumeration type and define a enumeration() method.
+For instance, suppose you had an enumeration of CPUs and a struct with it as
+a field:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">enum</span> <span class="n">CPUs</span> <span class="p">{</span>
+ <span class="n">cpu_x86_64</span> <span class="o">=</span> <span class="mi">5</span><span class="p">,</span>
+ <span class="n">cpu_x86</span> <span class="o">=</span> <span class="mi">7</span><span class="p">,</span>
+ <span class="n">cpu_PowerPC</span> <span class="o">=</span> <span class="mi">8</span>
+<span class="p">};</span>
+
+<span class="k">struct</span> <span class="n">Info</span> <span class="p">{</span>
+ <span class="n">CPUs</span> <span class="n">cpu</span><span class="p">;</span>
+ <span class="kt">uint32_t</span> <span class="n">flags</span><span class="p">;</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>To support reading and writing of this enumeration, you can define a
+ScalarEnumerationTraits specialization on CPUs, which can then be used
+as a field type:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">ScalarEnumerationTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">ScalarEnumerationTraits</span><span class="o"><</span><span class="n">CPUs</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">enumeration</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">CPUs</span> <span class="o">&</span><span class="n">value</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">enumCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"x86_64"</span><span class="p">,</span> <span class="n">cpu_x86_64</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">enumCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"x86"</span><span class="p">,</span> <span class="n">cpu_x86</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">enumCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"PowerPC"</span><span class="p">,</span> <span class="n">cpu_PowerPC</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Info</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Info</span> <span class="o">&</span><span class="n">info</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"cpu"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">cpu</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapOptional</span><span class="p">(</span><span class="s">"flags"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">flags</span><span class="p">,</span> <span class="mi">0</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>When reading YAML, if the string found does not match any of the strings
+specified by enumCase() methods, an error is automatically generated.
+When writing YAML, if the value being written does not match any of the values
+specified by the enumCase() methods, a runtime assertion is triggered.</p>
+</div>
+<div class="section" id="bitvalue">
+<h3><a class="toc-backref" href="#id9">BitValue</a><a class="headerlink" href="#bitvalue" title="Permalink to this headline">¶</a></h3>
+<p>Another common data structure in C++ is a field where each bit has a unique
+meaning. This is often used in a âflagsâ field. YAML I/O has support for
+converting such fields to a flow sequence. For instance suppose you
+had the following bit flags defined:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">enum</span> <span class="p">{</span>
+ <span class="n">flagsPointy</span> <span class="o">=</span> <span class="mi">1</span>
+ <span class="n">flagsHollow</span> <span class="o">=</span> <span class="mi">2</span>
+ <span class="n">flagsFlat</span> <span class="o">=</span> <span class="mi">4</span>
+ <span class="n">flagsRound</span> <span class="o">=</span> <span class="mi">8</span>
+<span class="p">};</span>
+
+<span class="n">LLVM_YAML_STRONG_TYPEDEF</span><span class="p">(</span><span class="kt">uint32_t</span><span class="p">,</span> <span class="n">MyFlags</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>To support reading and writing of MyFlags, you specialize ScalarBitSetTraits<>
+on MyFlags and provide the bit values and their names.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">ScalarBitSetTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">ScalarBitSetTraits</span><span class="o"><</span><span class="n">MyFlags</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">bitset</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MyFlags</span> <span class="o">&</span><span class="n">value</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"hollow"</span><span class="p">,</span> <span class="n">flagHollow</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"flat"</span><span class="p">,</span> <span class="n">flagFlat</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"round"</span><span class="p">,</span> <span class="n">flagRound</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"pointy"</span><span class="p">,</span> <span class="n">flagPointy</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+
+<span class="k">struct</span> <span class="n">Info</span> <span class="p">{</span>
+ <span class="n">StringRef</span> <span class="n">name</span><span class="p">;</span>
+ <span class="n">MyFlags</span> <span class="n">flags</span><span class="p">;</span>
+<span class="p">};</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Info</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Info</span><span class="o">&</span> <span class="n">info</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"name"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">name</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"flags"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">flags</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>With the above, YAML I/O (when writing) will test mask each value in the
+bitset trait against the flags field, and each that matches will
+cause the corresponding string to be added to the flow sequence. The opposite
+is done when reading and any unknown string values will result in a error. With
+the above schema, a same valid YAML document is:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+<span class="nt">flags</span><span class="p">:</span> <span class="p p-Indicator">[</span> <span class="nv">pointy</span><span class="p p-Indicator">,</span> <span class="nv">flat</span> <span class="p p-Indicator">]</span>
+</pre></div>
+</div>
+<p>Sometimes a âflagsâ field might contains an enumeration part
+defined by a bit-mask.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">enum</span> <span class="p">{</span>
+ <span class="n">flagsFeatureA</span> <span class="o">=</span> <span class="mi">1</span><span class="p">,</span>
+ <span class="n">flagsFeatureB</span> <span class="o">=</span> <span class="mi">2</span><span class="p">,</span>
+ <span class="n">flagsFeatureC</span> <span class="o">=</span> <span class="mi">4</span><span class="p">,</span>
+
+ <span class="n">flagsCPUMask</span> <span class="o">=</span> <span class="mi">24</span><span class="p">,</span>
+
+ <span class="n">flagsCPU1</span> <span class="o">=</span> <span class="mi">8</span><span class="p">,</span>
+ <span class="n">flagsCPU2</span> <span class="o">=</span> <span class="mi">16</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>To support reading and writing such fields, you need to use the maskedBitSet()
+method and provide the bit values, their names and the enumeration mask.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">ScalarBitSetTraits</span><span class="o"><</span><span class="n">MyFlags</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">bitset</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MyFlags</span> <span class="o">&</span><span class="n">value</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"featureA"</span><span class="p">,</span> <span class="n">flagsFeatureA</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"featureB"</span><span class="p">,</span> <span class="n">flagsFeatureB</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">bitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"featureC"</span><span class="p">,</span> <span class="n">flagsFeatureC</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">maskedBitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"CPU1"</span><span class="p">,</span> <span class="n">flagsCPU1</span><span class="p">,</span> <span class="n">flagsCPUMask</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">maskedBitSetCase</span><span class="p">(</span><span class="n">value</span><span class="p">,</span> <span class="s">"CPU2"</span><span class="p">,</span> <span class="n">flagsCPU2</span><span class="p">,</span> <span class="n">flagsCPUMask</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>YAML I/O (when writing) will apply the enumeration mask to the flags field,
+and compare the result and values from the bitset. As in case of a regular
+bitset, each that matches will cause the corresponding string to be added
+to the flow sequence.</p>
+</div>
+<div class="section" id="custom-scalar">
+<h3><a class="toc-backref" href="#id10">Custom Scalar</a><a class="headerlink" href="#custom-scalar" title="Permalink to this headline">¶</a></h3>
+<p>Sometimes for readability a scalar needs to be formatted in a custom way. For
+instance your internal data structure may use a integer for time (seconds since
+some epoch), but in YAML it would be much nicer to express that integer in
+some time format (e.g. 4-May-2012 10:30pm). YAML I/O has a way to support
+custom formatting and parsing of scalar types by specializing ScalarTraits<> on
+your data type. When writing, YAML I/O will provide the native type and
+your specialization must create a temporary llvm::StringRef. When reading,
+YAML I/O will provide an llvm::StringRef of scalar and your specialization
+must convert that to your native data type. An outline of a custom scalar type
+looks like:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">ScalarTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">ScalarTraits</span><span class="o"><</span><span class="n">MyCustomType</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">output</span><span class="p">(</span><span class="k">const</span> <span class="n">MyCustomType</span> <span class="o">&</span><span class="n">value</span><span class="p">,</span> <span class="kt">void</span><span class="o">*</span><span class="p">,</span>
+ <span class="n">llvm</span><span class="o">::</span><span class="n">raw_ostream</span> <span class="o">&</span><span class="n">out</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">out</span> <span class="o"><<</span> <span class="n">value</span><span class="p">;</span> <span class="c1">// do custom formatting here</span>
+ <span class="p">}</span>
+ <span class="k">static</span> <span class="n">StringRef</span> <span class="n">input</span><span class="p">(</span><span class="n">StringRef</span> <span class="n">scalar</span><span class="p">,</span> <span class="kt">void</span><span class="o">*</span><span class="p">,</span> <span class="n">MyCustomType</span> <span class="o">&</span><span class="n">value</span><span class="p">)</span> <span class="p">{</span>
+ <span class="c1">// do custom parsing here. Return the empty string on success,</span>
+ <span class="c1">// or an error message on failure.</span>
+ <span class="k">return</span> <span class="n">StringRef</span><span class="p">();</span>
+ <span class="p">}</span>
+ <span class="c1">// Determine if this scalar needs quotes.</span>
+ <span class="k">static</span> <span class="n">QuotingType</span> <span class="n">mustQuote</span><span class="p">(</span><span class="n">StringRef</span><span class="p">)</span> <span class="p">{</span> <span class="k">return</span> <span class="n">QuotingType</span><span class="o">::</span><span class="n">Single</span><span class="p">;</span> <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="block-scalars">
+<h3><a class="toc-backref" href="#id11">Block Scalars</a><a class="headerlink" href="#block-scalars" title="Permalink to this headline">¶</a></h3>
+<p>YAML block scalars are string literals that are represented in YAML using the
+literal block notation, just like the example shown below:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="nt">text</span><span class="p">:</span> <span class="p p-Indicator">|</span>
+ <span class="no">First line</span>
+ <span class="no">Second line</span>
+</pre></div>
+</div>
+<p>The YAML I/O library provides support for translating between YAML block scalars
+and specific C++ types by allowing you to specialize BlockScalarTraits<> on
+your data type. The library doesnât provide any built-in support for block
+scalar I/O for types like std::string and llvm::StringRef as they are already
+supported by YAML I/O and use the ordinary scalar notation by default.</p>
+<p>BlockScalarTraits specializations are very similar to the
+ScalarTraits specialization - YAML I/O will provide the native type and your
+specialization must create a temporary llvm::StringRef when writing, and
+it will also provide an llvm::StringRef that has the value of that block scalar
+and your specialization must convert that to your native data type when reading.
+An example of a custom type with an appropriate specialization of
+BlockScalarTraits is shown below:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">BlockScalarTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">struct</span> <span class="n">MyStringType</span> <span class="p">{</span>
+ <span class="n">std</span><span class="o">::</span><span class="n">string</span> <span class="n">Str</span><span class="p">;</span>
+<span class="p">};</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">BlockScalarTraits</span><span class="o"><</span><span class="n">MyStringType</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">output</span><span class="p">(</span><span class="k">const</span> <span class="n">MyStringType</span> <span class="o">&</span><span class="n">Value</span><span class="p">,</span> <span class="kt">void</span> <span class="o">*</span><span class="n">Ctxt</span><span class="p">,</span>
+ <span class="n">llvm</span><span class="o">::</span><span class="n">raw_ostream</span> <span class="o">&</span><span class="n">OS</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">OS</span> <span class="o"><<</span> <span class="n">Value</span><span class="p">.</span><span class="n">Str</span><span class="p">;</span>
+ <span class="p">}</span>
+
+ <span class="k">static</span> <span class="n">StringRef</span> <span class="n">input</span><span class="p">(</span><span class="n">StringRef</span> <span class="n">Scalar</span><span class="p">,</span> <span class="kt">void</span> <span class="o">*</span><span class="n">Ctxt</span><span class="p">,</span>
+ <span class="n">MyStringType</span> <span class="o">&</span><span class="n">Value</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">Value</span><span class="p">.</span><span class="n">Str</span> <span class="o">=</span> <span class="n">Scalar</span><span class="p">.</span><span class="n">str</span><span class="p">();</span>
+ <span class="k">return</span> <span class="nf">StringRef</span><span class="p">();</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="mappings">
+<h2><a class="toc-backref" href="#id12">Mappings</a><a class="headerlink" href="#mappings" title="Permalink to this headline">¶</a></h2>
+<p>To be translated to or from a YAML mapping for your type T you must specialize
+llvm::yaml::MappingTraits on T and implement the âvoid mapping(IO &io, T&)â
+method. If your native data structures use pointers to a class everywhere,
+you can specialize on the class pointer. Examples:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="c1">// Example of struct Foo which is used by value</span>
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Foo</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Foo</span> <span class="o">&</span><span class="n">foo</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapOptional</span><span class="p">(</span><span class="s">"size"</span><span class="p">,</span> <span class="n">foo</span><span class="p">.</span><span class="n">size</span><span class="p">);</span>
+ <span class="p">...</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+
+<span class="c1">// Example of struct Bar which is natively always a pointer</span>
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Bar</span><span class="o">*></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Bar</span> <span class="o">*&</span><span class="n">bar</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapOptional</span><span class="p">(</span><span class="s">"size"</span><span class="p">,</span> <span class="n">bar</span><span class="o">-></span><span class="n">size</span><span class="p">);</span>
+ <span class="p">...</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<div class="section" id="no-normalization">
+<h3><a class="toc-backref" href="#id13">No Normalization</a><a class="headerlink" href="#no-normalization" title="Permalink to this headline">¶</a></h3>
+<p>The mapping() method is responsible, if needed, for normalizing and
+denormalizing. In a simple case where the native data structure requires no
+normalization, the mapping method just uses mapOptional() or mapRequired() to
+bind the structâs fields to YAML key names. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Person</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Person</span> <span class="o">&</span><span class="n">info</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"name"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">name</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapOptional</span><span class="p">(</span><span class="s">"hat-size"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">hatSize</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="normalization">
+<h3><a class="toc-backref" href="#id14">Normalization</a><a class="headerlink" href="#normalization" title="Permalink to this headline">¶</a></h3>
+<p>When [de]normalization is required, the mapping() method needs a way to access
+normalized values as fields. To help with this, there is
+a template MappingNormalization<> which you can then use to automatically
+do the normalization and denormalization. The template is used to create
+a local variable in your mapping() method which contains the normalized keys.</p>
+<p>Suppose you have native data type
+Polar which specifies a position in polar coordinates (distance, angle):</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">struct</span> <span class="n">Polar</span> <span class="p">{</span>
+ <span class="kt">float</span> <span class="n">distance</span><span class="p">;</span>
+ <span class="kt">float</span> <span class="n">angle</span><span class="p">;</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>but youâve decided the normalized YAML for should be in x,y coordinates. That
+is, you want the yaml to look like:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="nt">x</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">10.3</span>
+<span class="nt">y</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">-4.7</span>
+</pre></div>
+</div>
+<p>You can support this by defining a MappingTraits that normalizes the polar
+coordinates to x,y coordinates when writing YAML and denormalizes x,y
+coordinates into polar when reading YAML.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Polar</span><span class="o">></span> <span class="p">{</span>
+
+ <span class="k">class</span> <span class="nc">NormalizedPolar</span> <span class="p">{</span>
+ <span class="k">public</span><span class="o">:</span>
+ <span class="n">NormalizedPolar</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">)</span>
+ <span class="o">:</span> <span class="n">x</span><span class="p">(</span><span class="mf">0.0</span><span class="p">),</span> <span class="n">y</span><span class="p">(</span><span class="mf">0.0</span><span class="p">)</span> <span class="p">{</span>
+ <span class="p">}</span>
+ <span class="n">NormalizedPolar</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="p">,</span> <span class="n">Polar</span> <span class="o">&</span><span class="n">polar</span><span class="p">)</span>
+ <span class="o">:</span> <span class="n">x</span><span class="p">(</span><span class="n">polar</span><span class="p">.</span><span class="n">distance</span> <span class="o">*</span> <span class="n">cos</span><span class="p">(</span><span class="n">polar</span><span class="p">.</span><span class="n">angle</span><span class="p">)),</span>
+ <span class="n">y</span><span class="p">(</span><span class="n">polar</span><span class="p">.</span><span class="n">distance</span> <span class="o">*</span> <span class="n">sin</span><span class="p">(</span><span class="n">polar</span><span class="p">.</span><span class="n">angle</span><span class="p">))</span> <span class="p">{</span>
+ <span class="p">}</span>
+ <span class="n">Polar</span> <span class="n">denormalize</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">return</span> <span class="n">Polar</span><span class="p">(</span><span class="n">sqrt</span><span class="p">(</span><span class="n">x</span><span class="o">*</span><span class="n">x</span><span class="o">+</span><span class="n">y</span><span class="o">*</span><span class="n">y</span><span class="p">),</span> <span class="n">arctan</span><span class="p">(</span><span class="n">x</span><span class="p">,</span><span class="n">y</span><span class="p">));</span>
+ <span class="p">}</span>
+
+ <span class="kt">float</span> <span class="n">x</span><span class="p">;</span>
+ <span class="kt">float</span> <span class="n">y</span><span class="p">;</span>
+ <span class="p">};</span>
+
+ <span class="k">static</span> <span class="kt">void</span> <span class="nf">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Polar</span> <span class="o">&</span><span class="n">polar</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">MappingNormalization</span><span class="o"><</span><span class="n">NormalizedPolar</span><span class="p">,</span> <span class="n">Polar</span><span class="o">></span> <span class="n">keys</span><span class="p">(</span><span class="n">io</span><span class="p">,</span> <span class="n">polar</span><span class="p">);</span>
+
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"x"</span><span class="p">,</span> <span class="n">keys</span><span class="o">-></span><span class="n">x</span><span class="p">);</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"y"</span><span class="p">,</span> <span class="n">keys</span><span class="o">-></span><span class="n">y</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>When writing YAML, the local variable âkeysâ will be a stack allocated
+instance of NormalizedPolar, constructed from the supplied polar object which
+initializes it x and y fields. The mapRequired() methods then write out the x
+and y values as key/value pairs.</p>
+<p>When reading YAML, the local variable âkeysâ will be a stack allocated instance
+of NormalizedPolar, constructed by the empty constructor. The mapRequired
+methods will find the matching key in the YAML document and fill in the x and y
+fields of the NormalizedPolar object keys. At the end of the mapping() method
+when the local keys variable goes out of scope, the denormalize() method will
+automatically be called to convert the read values back to polar coordinates,
+and then assigned back to the second parameter to mapping().</p>
+<p>In some cases, the normalized class may be a subclass of the native type and
+could be returned by the denormalize() method, except that the temporary
+normalized instance is stack allocated. In these cases, the utility template
+MappingNormalizationHeap<> can be used instead. It just like
+MappingNormalization<> except that it heap allocates the normalized object
+when reading YAML. It never destroys the normalized object. The denormalize()
+method can this return âthisâ.</p>
+</div>
+<div class="section" id="default-values">
+<h3><a class="toc-backref" href="#id15">Default values</a><a class="headerlink" href="#default-values" title="Permalink to this headline">¶</a></h3>
+<p>Within a mapping() method, calls to io.mapRequired() mean that that key is
+required to exist when parsing YAML documents, otherwise YAML I/O will issue an
+error.</p>
+<p>On the other hand, keys registered with io.mapOptional() are allowed to not
+exist in the YAML document being read. So what value is put in the field
+for those optional keys?
+There are two steps to how those optional fields are filled in. First, the
+second parameter to the mapping() method is a reference to a native class. That
+native class must have a default constructor. Whatever value the default
+constructor initially sets for an optional field will be that fieldâs value.
+Second, the mapOptional() method has an optional third parameter. If provided
+it is the value that mapOptional() should set that field to if the YAML document
+does not have that key.</p>
+<p>There is one important difference between those two ways (default constructor
+and third parameter to mapOptional). When YAML I/O generates a YAML document,
+if the mapOptional() third parameter is used, if the actual value being written
+is the same as (using ==) the default value, then that key/value is not written.</p>
+</div>
+<div class="section" id="order-of-keys">
+<h3><a class="toc-backref" href="#id16">Order of Keys</a><a class="headerlink" href="#order-of-keys" title="Permalink to this headline">¶</a></h3>
+<p>When writing out a YAML document, the keys are written in the order that the
+calls to mapRequired()/mapOptional() are made in the mapping() method. This
+gives you a chance to write the fields in an order that a human reader of
+the YAML document would find natural. This may be different that the order
+of the fields in the native class.</p>
+<p>When reading in a YAML document, the keys in the document can be in any order,
+but they are processed in the order that the calls to mapRequired()/mapOptional()
+are made in the mapping() method. That enables some interesting
+functionality. For instance, if the first field bound is the cpu and the second
+field bound is flags, and the flags are cpu specific, you can programmatically
+switch how the flags are converted to and from YAML based on the cpu.
+This works for both reading and writing. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">struct</span> <span class="n">Info</span> <span class="p">{</span>
+ <span class="n">CPUs</span> <span class="n">cpu</span><span class="p">;</span>
+ <span class="kt">uint32_t</span> <span class="n">flags</span><span class="p">;</span>
+<span class="p">};</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Info</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Info</span> <span class="o">&</span><span class="n">info</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"cpu"</span><span class="p">,</span> <span class="n">info</span><span class="p">.</span><span class="n">cpu</span><span class="p">);</span>
+ <span class="c1">// flags must come after cpu for this to work when reading yaml</span>
+ <span class="k">if</span> <span class="p">(</span> <span class="n">info</span><span class="p">.</span><span class="n">cpu</span> <span class="o">==</span> <span class="n">cpu_x86_64</span> <span class="p">)</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"flags"</span><span class="p">,</span> <span class="o">*</span><span class="p">(</span><span class="n">My86_64Flags</span><span class="o">*</span><span class="p">)</span><span class="n">info</span><span class="p">.</span><span class="n">flags</span><span class="p">);</span>
+ <span class="k">else</span>
+ <span class="n">io</span><span class="p">.</span><span class="n">mapRequired</span><span class="p">(</span><span class="s">"flags"</span><span class="p">,</span> <span class="o">*</span><span class="p">(</span><span class="n">My86Flags</span><span class="o">*</span><span class="p">)</span><span class="n">info</span><span class="p">.</span><span class="n">flags</span><span class="p">);</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="tags">
+<h3><a class="toc-backref" href="#id17">Tags</a><a class="headerlink" href="#tags" title="Permalink to this headline">¶</a></h3>
+<p>The YAML syntax supports tags as a way to specify the type of a node before
+it is parsed. This allows dynamic types of nodes. But the YAML I/O model uses
+static typing, so there are limits to how you can use tags with the YAML I/O
+model. Recently, we added support to YAML I/O for checking/setting the optional
+tag on a map. Using this functionality it is even possbile to support different
+mappings, as long as they are convertible.</p>
+<p>To check a tag, inside your mapping() method you can use io.mapTag() to specify
+what the tag should be. This will also add that tag when writing yaml.</p>
+</div>
+<div class="section" id="validation">
+<h3><a class="toc-backref" href="#id18">Validation</a><a class="headerlink" href="#validation" title="Permalink to this headline">¶</a></h3>
+<p>Sometimes in a yaml map, each key/value pair is valid, but the combination is
+not. This is similar to something having no syntax errors, but still having
+semantic errors. To support semantic level checking, YAML I/O allows
+an optional <code class="docutils literal notranslate"><span class="pre">validate()</span></code> method in a MappingTraits template specialization.</p>
+<p>When parsing yaml, the <code class="docutils literal notranslate"><span class="pre">validate()</span></code> method is call <em>after</em> all key/values in
+the map have been processed. Any error message returned by the <code class="docutils literal notranslate"><span class="pre">validate()</span></code>
+method during input will be printed just a like a syntax error would be printed.
+When writing yaml, the <code class="docutils literal notranslate"><span class="pre">validate()</span></code> method is called <em>before</em> the yaml
+key/values are written. Any error during output will trigger an <code class="docutils literal notranslate"><span class="pre">assert()</span></code>
+because it is a programming error to have invalid struct values.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">struct</span> <span class="n">Stuff</span> <span class="p">{</span>
+ <span class="p">...</span>
+<span class="p">};</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Stuff</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Stuff</span> <span class="o">&</span><span class="n">stuff</span><span class="p">)</span> <span class="p">{</span>
+ <span class="p">...</span>
+ <span class="p">}</span>
+ <span class="k">static</span> <span class="n">StringRef</span> <span class="n">validate</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Stuff</span> <span class="o">&</span><span class="n">stuff</span><span class="p">)</span> <span class="p">{</span>
+ <span class="c1">// Look at all fields in 'stuff' and if there</span>
+ <span class="c1">// are any bad values return a string describing</span>
+ <span class="c1">// the error. Otherwise return an empty string.</span>
+ <span class="k">return</span> <span class="n">StringRef</span><span class="p">();</span>
+ <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="flow-mapping">
+<h3><a class="toc-backref" href="#id19">Flow Mapping</a><a class="headerlink" href="#flow-mapping" title="Permalink to this headline">¶</a></h3>
+<p>A YAML âflow mappingâ is a mapping that uses the inline notation
+(e.g { x: 1, y: 0 } ) when written to YAML. To specify that a type should be
+written in YAML using flow mapping, your MappingTraits specialization should
+add âstatic const bool flow = true;â. For instance:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">MappingTraits</span><span class="p">;</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">IO</span><span class="p">;</span>
+
+<span class="k">struct</span> <span class="n">Stuff</span> <span class="p">{</span>
+ <span class="p">...</span>
+<span class="p">};</span>
+
+<span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">MappingTraits</span><span class="o"><</span><span class="n">Stuff</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">void</span> <span class="n">mapping</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">Stuff</span> <span class="o">&</span><span class="n">stuff</span><span class="p">)</span> <span class="p">{</span>
+ <span class="p">...</span>
+ <span class="p">}</span>
+
+ <span class="k">static</span> <span class="k">const</span> <span class="kt">bool</span> <span class="n">flow</span> <span class="o">=</span> <span class="nb">true</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>Flow mappings are subject to line wrapping according to the Output object
+configuration.</p>
+</div>
+</div>
+<div class="section" id="sequence">
+<h2><a class="toc-backref" href="#id20">Sequence</a><a class="headerlink" href="#sequence" title="Permalink to this headline">¶</a></h2>
+<p>To be translated to or from a YAML sequence for your type T you must specialize
+llvm::yaml::SequenceTraits on T and implement two methods:
+<code class="docutils literal notranslate"><span class="pre">size_t</span> <span class="pre">size(IO</span> <span class="pre">&io,</span> <span class="pre">T&)</span></code> and
+<code class="docutils literal notranslate"><span class="pre">T::value_type&</span> <span class="pre">element(IO</span> <span class="pre">&io,</span> <span class="pre">T&,</span> <span class="pre">size_t</span> <span class="pre">indx)</span></code>. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">SequenceTraits</span><span class="o"><</span><span class="n">MySeq</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">size_t</span> <span class="n">size</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MySeq</span> <span class="o">&</span><span class="n">list</span><span class="p">)</span> <span class="p">{</span> <span class="p">...</span> <span class="p">}</span>
+ <span class="k">static</span> <span class="n">MySeqEl</span> <span class="o">&</span><span class="n">element</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MySeq</span> <span class="o">&</span><span class="n">list</span><span class="p">,</span> <span class="kt">size_t</span> <span class="n">index</span><span class="p">)</span> <span class="p">{</span> <span class="p">...</span> <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>The size() method returns how many elements are currently in your sequence.
+The element() method returns a reference to the iâth element in the sequence.
+When parsing YAML, the element() method may be called with an index one bigger
+than the current size. Your element() method should allocate space for one
+more element (using default constructor if element is a C++ object) and returns
+a reference to that new allocated space.</p>
+<div class="section" id="flow-sequence">
+<h3><a class="toc-backref" href="#id21">Flow Sequence</a><a class="headerlink" href="#flow-sequence" title="Permalink to this headline">¶</a></h3>
+<p>A YAML âflow sequenceâ is a sequence that when written to YAML it uses the
+inline notation (e.g [ foo, bar ] ). To specify that a sequence type should
+be written in YAML as a flow sequence, your SequenceTraits specialization should
+add âstatic const bool flow = true;â. For instance:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">SequenceTraits</span><span class="o"><</span><span class="n">MyList</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">size_t</span> <span class="n">size</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MyList</span> <span class="o">&</span><span class="n">list</span><span class="p">)</span> <span class="p">{</span> <span class="p">...</span> <span class="p">}</span>
+ <span class="k">static</span> <span class="n">MyListEl</span> <span class="o">&</span><span class="n">element</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MyList</span> <span class="o">&</span><span class="n">list</span><span class="p">,</span> <span class="kt">size_t</span> <span class="n">index</span><span class="p">)</span> <span class="p">{</span> <span class="p">...</span> <span class="p">}</span>
+
+ <span class="c1">// The existence of this member causes YAML I/O to use a flow sequence</span>
+ <span class="k">static</span> <span class="k">const</span> <span class="kt">bool</span> <span class="n">flow</span> <span class="o">=</span> <span class="nb">true</span><span class="p">;</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+<p>With the above, if you used MyList as the data type in your native data
+structures, then when converted to YAML, a flow sequence of integers
+will be used (e.g. [ 10, -3, 4 ]).</p>
+<p>Flow sequences are subject to line wrapping according to the Output object
+configuration.</p>
+</div>
+<div class="section" id="utility-macros">
+<h3><a class="toc-backref" href="#id22">Utility Macros</a><a class="headerlink" href="#utility-macros" title="Permalink to this headline">¶</a></h3>
+<p>Since a common source of sequences is std::vector<>, YAML I/O provides macros:
+LLVM_YAML_IS_SEQUENCE_VECTOR() and LLVM_YAML_IS_FLOW_SEQUENCE_VECTOR() which
+can be used to easily specify SequenceTraits<> on a std::vector type. YAML
+I/O does not partial specialize SequenceTraits on std::vector<> because that
+would force all vectors to be sequences. An example use of the macros:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="n">std</span><span class="o">::</span><span class="n">vector</span><span class="o"><</span><span class="n">MyType1</span><span class="o">></span><span class="p">;</span>
+<span class="n">std</span><span class="o">::</span><span class="n">vector</span><span class="o"><</span><span class="n">MyType2</span><span class="o">></span><span class="p">;</span>
+<span class="n">LLVM_YAML_IS_SEQUENCE_VECTOR</span><span class="p">(</span><span class="n">MyType1</span><span class="p">)</span>
+<span class="n">LLVM_YAML_IS_FLOW_SEQUENCE_VECTOR</span><span class="p">(</span><span class="n">MyType2</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="document-list">
+<h2><a class="toc-backref" href="#id23">Document List</a><a class="headerlink" href="#document-list" title="Permalink to this headline">¶</a></h2>
+<p>YAML allows you to define multiple âdocumentsâ in a single YAML file. Each
+new document starts with a left aligned âââ token. The end of all documents
+is denoted with a left aligned ââ¦â token. Many users of YAML will never
+have need for multiple documents. The top level node in their YAML schema
+will be a mapping or sequence. For those cases, the following is not needed.
+But for cases where you do want multiple documents, you can specify a
+trait for you document list type. The trait has the same methods as
+SequenceTraits but is named DocumentListTraits. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">template</span> <span class="o"><></span>
+<span class="k">struct</span> <span class="n">DocumentListTraits</span><span class="o"><</span><span class="n">MyDocList</span><span class="o">></span> <span class="p">{</span>
+ <span class="k">static</span> <span class="kt">size_t</span> <span class="n">size</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MyDocList</span> <span class="o">&</span><span class="n">list</span><span class="p">)</span> <span class="p">{</span> <span class="p">...</span> <span class="p">}</span>
+ <span class="k">static</span> <span class="n">MyDocType</span> <span class="n">element</span><span class="p">(</span><span class="n">IO</span> <span class="o">&</span><span class="n">io</span><span class="p">,</span> <span class="n">MyDocList</span> <span class="o">&</span><span class="n">list</span><span class="p">,</span> <span class="kt">size_t</span> <span class="n">index</span><span class="p">)</span> <span class="p">{</span> <span class="p">...</span> <span class="p">}</span>
+<span class="p">};</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="user-context-data">
+<h2><a class="toc-backref" href="#id24">User Context Data</a><a class="headerlink" href="#user-context-data" title="Permalink to this headline">¶</a></h2>
+<p>When an llvm::yaml::Input or llvm::yaml::Output object is created their
+constructors take an optional âcontextâ parameter. This is a pointer to
+whatever state information you might need.</p>
+<p>For instance, in a previous example we showed how the conversion type for a
+flags field could be determined at runtime based on the value of another field
+in the mapping. But what if an inner mapping needs to know some field value
+of an outer mapping? That is where the âcontextâ parameter comes in. You
+can set values in the context in the outer mapâs mapping() method and
+retrieve those values in the inner mapâs mapping() method.</p>
+<p>The context value is just a void*. All your traits which use the context
+and operate on your native data types, need to agree what the context value
+actually is. It could be a pointer to an object or struct which your various
+traits use to shared context sensitive information.</p>
+</div>
+<div class="section" id="output">
+<h2><a class="toc-backref" href="#id25">Output</a><a class="headerlink" href="#output" title="Permalink to this headline">¶</a></h2>
+<p>The llvm::yaml::Output class is used to generate a YAML document from your
+in-memory data structures, using traits defined on your data types.
+To instantiate an Output object you need an llvm::raw_ostream, an optional
+context pointer and an optional wrapping column:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">class</span> <span class="nc">Output</span> <span class="o">:</span> <span class="k">public</span> <span class="n">IO</span> <span class="p">{</span>
+<span class="k">public</span><span class="o">:</span>
+ <span class="n">Output</span><span class="p">(</span><span class="n">llvm</span><span class="o">::</span><span class="n">raw_ostream</span> <span class="o">&</span><span class="p">,</span> <span class="kt">void</span> <span class="o">*</span><span class="n">context</span> <span class="o">=</span> <span class="nb">NULL</span><span class="p">,</span> <span class="kt">int</span> <span class="n">WrapColumn</span> <span class="o">=</span> <span class="mi">70</span><span class="p">);</span>
+</pre></div>
+</div>
+<p>Once you have an Output object, you can use the C++ stream operator on it
+to write your native data as YAML. One thing to recall is that a YAML file
+can contain multiple âdocumentsâ. If the top level data structure you are
+streaming as YAML is a mapping, scalar, or sequence, then Output assumes you
+are generating one document and wraps the mapping output
+with â<code class="docutils literal notranslate"><span class="pre">---</span></code>â and trailing â<code class="docutils literal notranslate"><span class="pre">...</span></code>â.</p>
+<p>The WrapColumn parameter will cause the flow mappings and sequences to
+line-wrap when they go over the supplied column. Pass 0 to completely
+suppress the wrapping.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">Output</span><span class="p">;</span>
+
+<span class="kt">void</span> <span class="nf">dumpMyMapDoc</span><span class="p">(</span><span class="k">const</span> <span class="n">MyMapType</span> <span class="o">&</span><span class="n">info</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">Output</span> <span class="n">yout</span><span class="p">(</span><span class="n">llvm</span><span class="o">::</span><span class="n">outs</span><span class="p">());</span>
+ <span class="n">yout</span> <span class="o"><<</span> <span class="n">info</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>The above could produce output like:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="nn">---</span>
+<span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+<span class="nt">hat-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">7</span>
+<span class="nn">...</span>
+</pre></div>
+</div>
+<p>On the other hand, if the top level data structure you are streaming as YAML
+has a DocumentListTraits specialization, then Output walks through each element
+of your DocumentList and generates a âââ before the start of each element
+and ends with a ââ¦â.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">Output</span><span class="p">;</span>
+
+<span class="kt">void</span> <span class="nf">dumpMyMapDoc</span><span class="p">(</span><span class="k">const</span> <span class="n">MyDocListType</span> <span class="o">&</span><span class="n">docList</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">Output</span> <span class="n">yout</span><span class="p">(</span><span class="n">llvm</span><span class="o">::</span><span class="n">outs</span><span class="p">());</span>
+ <span class="n">yout</span> <span class="o"><<</span> <span class="n">docList</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>The above could produce output like:</p>
+<div class="highlight-yaml notranslate"><div class="highlight"><pre><span></span><span class="nn">---</span>
+<span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+<span class="nt">hat-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">7</span>
+<span class="nn">---</span>
+<span class="nt">name</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">Tom</span>
+<span class="nt">shoe-size</span><span class="p">:</span> <span class="l l-Scalar l-Scalar-Plain">11</span>
+<span class="nn">...</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="input">
+<h2><a class="toc-backref" href="#id26">Input</a><a class="headerlink" href="#input" title="Permalink to this headline">¶</a></h2>
+<p>The llvm::yaml::Input class is used to parse YAML document(s) into your native
+data structures. To instantiate an Input
+object you need a StringRef to the entire YAML file, and optionally a context
+pointer:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">class</span> <span class="nc">Input</span> <span class="o">:</span> <span class="k">public</span> <span class="n">IO</span> <span class="p">{</span>
+<span class="k">public</span><span class="o">:</span>
+ <span class="n">Input</span><span class="p">(</span><span class="n">StringRef</span> <span class="n">inputContent</span><span class="p">,</span> <span class="kt">void</span> <span class="o">*</span><span class="n">context</span><span class="o">=</span><span class="nb">NULL</span><span class="p">);</span>
+</pre></div>
+</div>
+<p>Once you have an Input object, you can use the C++ stream operator to read
+the document(s). If you expect there might be multiple YAML documents in
+one file, youâll need to specialize DocumentListTraits on a list of your
+document type and stream in that document list type. Otherwise you can
+just stream in the document type. Also, you can check if there was
+any syntax errors in the YAML be calling the error() method on the Input
+object. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="c1">// Reading a single document</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">Input</span><span class="p">;</span>
+
+<span class="n">Input</span> <span class="nf">yin</span><span class="p">(</span><span class="n">mb</span><span class="p">.</span><span class="n">getBuffer</span><span class="p">());</span>
+
+<span class="c1">// Parse the YAML file</span>
+<span class="n">MyDocType</span> <span class="n">theDoc</span><span class="p">;</span>
+<span class="n">yin</span> <span class="o">>></span> <span class="n">theDoc</span><span class="p">;</span>
+
+<span class="c1">// Check for error</span>
+<span class="k">if</span> <span class="p">(</span> <span class="n">yin</span><span class="p">.</span><span class="n">error</span><span class="p">()</span> <span class="p">)</span>
+ <span class="k">return</span><span class="p">;</span>
+</pre></div>
+</div>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="c1">// Reading multiple documents in one file</span>
+<span class="k">using</span> <span class="n">llvm</span><span class="o">::</span><span class="n">yaml</span><span class="o">::</span><span class="n">Input</span><span class="p">;</span>
+
+<span class="n">LLVM_YAML_IS_DOCUMENT_LIST_VECTOR</span><span class="p">(</span><span class="n">MyDocType</span><span class="p">)</span>
+
+<span class="n">Input</span> <span class="n">yin</span><span class="p">(</span><span class="n">mb</span><span class="p">.</span><span class="n">getBuffer</span><span class="p">());</span>
+
+<span class="c1">// Parse the YAML file</span>
+<span class="n">std</span><span class="o">::</span><span class="n">vector</span><span class="o"><</span><span class="n">MyDocType</span><span class="o">></span> <span class="n">theDocList</span><span class="p">;</span>
+<span class="n">yin</span> <span class="o">>></span> <span class="n">theDocList</span><span class="p">;</span>
+
+<span class="c1">// Check for error</span>
+<span class="k">if</span> <span class="p">(</span> <span class="n">yin</span><span class="p">.</span><span class="n">error</span><span class="p">()</span> <span class="p">)</span>
+ <span class="k">return</span><span class="p">;</span>
+</pre></div>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="genindex.html" title="General Index"
+ >index</a></li>
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--- www-releases/trunk/9.0.0/docs/_sources/AMDGPU/AMDGPUAsmGFX10.rst.txt (added)
+++ www-releases/trunk/9.0.0/docs/_sources/AMDGPU/AMDGPUAsmGFX10.rst.txt Thu Sep 19 07:32:46 2019
@@ -0,0 +1,2176 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+============================
+Syntax of GFX10 Instructions
+============================
+
+.. contents::
+ :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DPP16
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+
+DPP8
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mac_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid10_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid10_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop
+ ds_or_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata128_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata96_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata32_0>`, :ref:`vdata1<amdgpu_synid10_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata0<amdgpu_synid10_vdata64_0>`, :ref:`vdata1<amdgpu_synid10_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid10_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ exp :ref:`tgt<amdgpu_synid10_tgt>`, :ref:`vsrc0<amdgpu_synid10_src_exp>`, :ref:`vsrc1<amdgpu_synid10_src_exp>`, :ref:`vsrc2<amdgpu_synid10_src_exp>`, :ref:`vsrc3<amdgpu_synid10_src_exp>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f32x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`f64x2<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_addr_flat>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata64_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata96_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata128_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid10_addr_flat>`, :ref:`vdata<amdgpu_synid10_vdata32_0>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dword :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_sshort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_load_ushort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_byte :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dword :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_short :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid10_vdst96_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid10_vdst128_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_and :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid10_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_or :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_gather4 :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_get_lod :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_sample :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid10_data_mimg_store>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_store_pck :ref:`vdata<amdgpu_synid10_data_mimg_store>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_gl0_inv
+ buffer_gl1_inv
+ buffer_load_dword :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+SDWA
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f16_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32_sdwa :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sub_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`vcc<amdgpu_synid10_vcc_32>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+SMEM
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`imm3<amdgpu_synid10_perm_smem>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+ s_atc_probe_buffer :ref:`imm3<amdgpu_synid10_perm_smem>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>`
+ s_atomic_add :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid10_sdst512_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid10_sdst128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid10_sdst256_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid10_sdata32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid10_sdata64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid10_sdata128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`, :ref:`soffset<amdgpu_synid10_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+ s_dcache_inv
+ s_dcache_wb
+ s_get_waveid_in_workgroup :ref:`sdst<amdgpu_synid10_sdst32_0>`
+ s_gl1_inv
+ s_load_dword :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid10_sdst512_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid10_sdst128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid10_sdst256_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid10_sdst64_0>`
+ s_memtime :ref:`sdst<amdgpu_synid10_sdst64_0>`
+ s_scratch_load_dword :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid10_sdst128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid10_sdata32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid10_sdata64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid10_sdata128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_scratch>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dword :ref:`sdata<amdgpu_synid10_sdata32_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid10_sdata64_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid10_sdata128_0>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`, :ref:`soffset<amdgpu_synid10_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_and_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn1_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn1_wrexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn2_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_andn2_wrexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_1>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_movrelsd_2_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_1>`
+ s_nand_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_nor_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_not_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_not_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_or_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_orn1_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_orn2_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_xnor_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+ s_xor_saveexec_b32 :ref:`sdst<amdgpu_synid10_sdst32_0>`, :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid10_sdst64_0>`, :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_absdiff_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_add_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_and_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_and_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_max_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_max_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_min_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_min_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_or_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_or_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_call_b64 :ref:`sdst<amdgpu_synid10_sdst64_1>`, :ref:`label<amdgpu_synid10_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_uimm16>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`hwreg<amdgpu_synid10_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`imm16<amdgpu_synid10_simm16>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid10_hwreg>`, :ref:`ssrc<amdgpu_synid10_ssrc32_2>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid10_hwreg>`, :ref:`imm32<amdgpu_synid10_bimm32>`
+ s_subvector_loop_begin :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`label<amdgpu_synid10_label>`
+ s_subvector_loop_end :ref:`sdst<amdgpu_synid10_sdst32_1>`, :ref:`label<amdgpu_synid10_label>`
+ s_version :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_expcnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_lgkmcnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_vmcnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt_vscnt :ref:`ssrc<amdgpu_synid10_ssrc32_2>`, :ref:`imm16<amdgpu_synid10_bimm16>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid10_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid10_label>`
+ s_clause :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_code_end
+ s_decperflevel :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_denorm_mode :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_endpgm
+ s_endpgm_ordered_ps_done
+ s_endpgm_saved
+ s_icache_inv
+ s_incperflevel :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_inst_prefetch :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_nop :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_round_mode :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_sendmsg :ref:`msg<amdgpu_synid10_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid10_msg>`
+ s_sethalt :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_setkill :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_setprio :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_sleep :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_trap :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_ttracedata
+ s_ttracedata_imm :ref:`imm16<amdgpu_synid10_bimm16>`
+ s_waitcnt :ref:`waitcnt<amdgpu_synid10_waitcnt>`
+ s_wakeup
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`param<amdgpu_synid10_param>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_clrexcp
+ v_cos_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_log_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_log_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movreld_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movrels_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_2_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_pipeflush
+ v_rcp_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid10_sdst32_2>`, :ref:`vsrc<amdgpu_synid10_vsrc32_1>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_swaprel_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_add_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_add_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_add_nc_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_and_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_fmaak_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`imm32<amdgpu_synid10_fimm16>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`imm32<amdgpu_synid10_fimm32>`
+ v_fmac_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_fmamk_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`imm32<amdgpu_synid10_fimm16>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`imm32<amdgpu_synid10_fimm32>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mac_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mac_legacy_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_madak_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`imm32<amdgpu_synid10_fimm32>`
+ v_madmk_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`imm32<amdgpu_synid10_fimm32>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+ v_max_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_max_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_max_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_max_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_min_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_or_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_sub_co_ci_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_sub_nc_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_subrev_co_ci_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_subrev_nc_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_add_co_ci_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_co_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_add_nc_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_add_nc_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_clrexcp_e64
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_eq_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_eq_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_eq_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_f_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_f_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_f_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_f_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ge_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ge_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ge_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_gt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_gt_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_gt_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_le_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_le_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_le_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_lg_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_lt_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_lt_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ne_i16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_ne_u16_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_ne_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_neq_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_t_i64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_t_u32_e64 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cmpx_t_u64_e64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_cmpx_tru_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`src1<amdgpu_synid10_src64_0>`, :ref:`src2<amdgpu_synid10_src64_0>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid10_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p2_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i16<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src64_0>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`i64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`u64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_max_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_min_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_movrels_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_2_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b128<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`vsrc2<amdgpu_synid10_vsrc128_0>`::ref:`b128<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_mullit_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_nop_e64
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_permlane16_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`, :ref:`ssrc2<amdgpu_synid10_ssrc32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_permlanex16_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`, :ref:`ssrc2<amdgpu_synid10_ssrc32_3>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_pipeflush_e64
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid10_sdst32_2>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_ci_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_nc_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_i32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_sub_nc_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`ssrc2<amdgpu_synid10_wssrc>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_nc_u32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`, :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid10_vdst64_0>`, :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`ssrc0<amdgpu_synid10_ssrc32_5>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+ v_xor3_b32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`
+
+VOP3P
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>`, :ref:`src2<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`src1<amdgpu_synid10_src32_2>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_class_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_class_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+ v_cmpx_eq_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_eq_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_eq_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_eq_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_f_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_f_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_f_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_f_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ge_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ge_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ge_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ge_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_gt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_gt_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_gt_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_gt_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_le_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_le_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_le_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_le_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lg_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lg_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lg_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lt_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_lt_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_lt_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ne_i16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ne_u16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ne_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_neq_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_neq_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_neq_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nge_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nge_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nge_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_ngt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ngt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_ngt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nle_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nle_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nle_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nlg_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlg_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlg_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_nlt_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlt_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_nlt_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_o_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_o_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_o_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_t_i32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_t_i64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_t_u32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_t_u64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_tru_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_tru_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_tru_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+ v_cmpx_u_f16 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_u_f32 :ref:`src0<amdgpu_synid10_src32_1>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+ v_cmpx_u_f64 :ref:`src0<amdgpu_synid10_src64_0>`, :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+ :hidden:
+
+ gfx10_attr
+ gfx10_bimm16
+ gfx10_bimm32
+ gfx10_fimm16
+ gfx10_fimm32
+ gfx10_hwreg
+ gfx10_label
+ gfx10_msg
+ gfx10_param
+ gfx10_perm_smem
+ gfx10_simm16
+ gfx10_tgt
+ gfx10_uimm16
+ gfx10_vcc_32
+ gfx10_waitcnt
+ gfx10_addr_buf
+ gfx10_addr_ds
+ gfx10_addr_flat
+ gfx10_addr_mimg
+ gfx10_base_smem_addr
+ gfx10_base_smem_buf
+ gfx10_base_smem_scratch
+ gfx10_data_buf_atomic128
+ gfx10_data_buf_atomic32
+ gfx10_data_buf_atomic64
+ gfx10_data_mimg_atomic_cmp
+ gfx10_data_mimg_atomic_reg
+ gfx10_data_mimg_store
+ gfx10_data_mimg_store_d16
+ gfx10_data_smem_atomic128
+ gfx10_data_smem_atomic32
+ gfx10_data_smem_atomic64
+ gfx10_dst_buf_128
+ gfx10_dst_buf_32
+ gfx10_dst_buf_64
+ gfx10_dst_buf_96
+ gfx10_dst_buf_lds
+ gfx10_dst_flat_atomic32
+ gfx10_dst_flat_atomic64
+ gfx10_dst_mimg_gather4
+ gfx10_dst_mimg_regular
+ gfx10_dst_mimg_regular_d16
+ gfx10_offset_buf
+ gfx10_offset_smem_buf
+ gfx10_offset_smem_plain
+ gfx10_rsrc_buf
+ gfx10_rsrc_mimg
+ gfx10_saddr_flat_global
+ gfx10_saddr_flat_scratch
+ gfx10_samp_mimg
+ gfx10_sdata128_0
+ gfx10_sdata32_0
+ gfx10_sdata64_0
+ gfx10_sdst128_0
+ gfx10_sdst256_0
+ gfx10_sdst32_0
+ gfx10_sdst32_1
+ gfx10_sdst32_2
+ gfx10_sdst512_0
+ gfx10_sdst64_0
+ gfx10_sdst64_1
+ gfx10_src32_0
+ gfx10_src32_1
+ gfx10_src32_2
+ gfx10_src32_3
+ gfx10_src64_0
+ gfx10_src_exp
+ gfx10_ssrc32_0
+ gfx10_ssrc32_1
+ gfx10_ssrc32_2
+ gfx10_ssrc32_3
+ gfx10_ssrc32_4
+ gfx10_ssrc32_5
+ gfx10_ssrc64_0
+ gfx10_ssrc64_1
+ gfx10_vaddr_flat_global
+ gfx10_vaddr_flat_scratch
+ gfx10_vdata128_0
+ gfx10_vdata32_0
+ gfx10_vdata64_0
+ gfx10_vdata96_0
+ gfx10_vdst128_0
+ gfx10_vdst32_0
+ gfx10_vdst64_0
+ gfx10_vdst96_0
+ gfx10_vsrc128_0
+ gfx10_vsrc32_0
+ gfx10_vsrc32_1
+ gfx10_vsrc64_0
+ gfx10_wsdst
+ gfx10_wssrc
+ gfx10_mad_type_dev
+ gfx10_mod_dpp_sdwa_abs_neg
+ gfx10_mod_sdwa_sext
+ gfx10_mod_vop3_abs_neg
+ gfx10_opt
+ gfx10_ret
+ gfx10_type_dev
Added: www-releases/trunk/9.0.0/docs/_sources/AMDGPU/AMDGPUAsmGFX7.rst.txt
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/9.0.0/docs/_sources/AMDGPU/AMDGPUAsmGFX7.rst.txt?rev=372328&view=auto
==============================================================================
--- www-releases/trunk/9.0.0/docs/_sources/AMDGPU/AMDGPUAsmGFX7.rst.txt (added)
+++ www-releases/trunk/9.0.0/docs/_sources/AMDGPU/AMDGPUAsmGFX7.rst.txt Thu Sep 19 07:32:46 2019
@@ -0,0 +1,1417 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+============================
+Syntax of GFX7 Instructions
+============================
+
+.. contents::
+ :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_src2_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid7_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid7_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_f64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_i64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_f64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_i64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop
+ ds_or_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_src2_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid7_vdst128_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid7_vdst96_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata128_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata96_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_src2_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata32_0>`, :ref:`vdata1<amdgpu_synid7_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata0<amdgpu_synid7_vdata64_0>`, :ref:`vdata1<amdgpu_synid7_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_ds>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid7_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ exp :ref:`tgt<amdgpu_synid7_tgt>`, :ref:`vsrc0<amdgpu_synid7_src_exp>`, :ref:`vsrc1<amdgpu_synid7_src_exp>`, :ref:`vsrc2<amdgpu_synid7_src_exp>`, :ref:`vsrc3<amdgpu_synid7_src_exp>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`b32x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata128_0>`::ref:`b64x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`f32x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata128_0>`::ref:`f64x2<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmax :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`f32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`f64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmin :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`f32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`f64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`f64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`s32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`s64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`s32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`s64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`s64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>`::ref:`u64<amdgpu_synid7_type_dev>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`, :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid7_vdst96_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid7_vdst128_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vaddr<amdgpu_synid7_addr_flat>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata64_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata96_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata128_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid7_addr_flat>`, :ref:`vdata<amdgpu_synid7_vdata32_0>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_and :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid7_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_or :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4 :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_l :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_gather4_o :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_get_lod :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_l :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_lz :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_sample_o :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid7_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store :ref:`vdata<amdgpu_synid7_data_mimg_store>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_mip :ref:`vdata<amdgpu_synid7_data_mimg_store>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid7_data_mimg_store>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+ image_store_pck :ref:`vdata<amdgpu_synid7_data_mimg_store>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`, :ref:`srsrc<amdgpu_synid7_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic128>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dword :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid7_vdata32_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid7_vdata32_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid7_vdata64_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid7_vdata96_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid7_vdata128_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid7_vdata32_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid7_vdata64_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid7_vdata96_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid7_vdata128_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid7_vdata32_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_wbinvl1
+ buffer_wbinvl1_vol
+
+SMRD
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid7_sdst32_0>`, :ref:`sbase<amdgpu_synid7_base_smem_buf>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid7_sdst512_0>`, :ref:`sbase<amdgpu_synid7_base_smem_buf>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`sbase<amdgpu_synid7_base_smem_buf>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid7_sdst128_0>`, :ref:`sbase<amdgpu_synid7_base_smem_buf>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid7_sdst256_0>`, :ref:`sbase<amdgpu_synid7_base_smem_buf>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_dcache_inv
+ s_dcache_inv_vol
+ s_load_dword :ref:`sdst<amdgpu_synid7_sdst32_0>`, :ref:`sbase<amdgpu_synid7_base_smem_addr>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid7_sdst512_0>`, :ref:`sbase<amdgpu_synid7_base_smem_addr>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`sbase<amdgpu_synid7_base_smem_addr>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid7_sdst128_0>`, :ref:`sbase<amdgpu_synid7_base_smem_addr>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid7_sdst256_0>`, :ref:`sbase<amdgpu_synid7_base_smem_addr>`, :ref:`soffset<amdgpu_synid7_offset_smem>`
+ s_memtime :ref:`sdst<amdgpu_synid7_sdst64_0>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_cbranch_join :ref:`ssrc<amdgpu_synid7_ssrc32_1>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_mov_fed_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid7_sdst32_0>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_2>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_not_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_not_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_3>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_3>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_1>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_absdiff_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_add_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_add_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_and_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_and_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid7_ssrc64_2>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_2>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_max_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_max_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_min_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_min_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_or_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_or_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid7_sdst64_1>`, :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid7_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+ s_setvskip :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cbranch_i_fork :ref:`ssrc<amdgpu_synid7_ssrc64_3>`, :ref:`label<amdgpu_synid7_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid7_ssrc32_4>`, :ref:`imm16<amdgpu_synid7_uimm16>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`hwreg<amdgpu_synid7_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`imm16<amdgpu_synid7_simm16>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid7_hwreg>`, :ref:`ssrc<amdgpu_synid7_ssrc32_4>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid7_hwreg>`, :ref:`imm32<amdgpu_synid7_bimm32>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid7_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid7_label>`
+ s_decperflevel :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_endpgm
+ s_icache_inv
+ s_incperflevel :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_nop :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_sendmsg :ref:`msg<amdgpu_synid7_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid7_msg>`
+ s_sethalt :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_setkill :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_setprio :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_sleep :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_trap :ref:`imm16<amdgpu_synid7_bimm16>`
+ s_ttracedata
+ s_waitcnt :ref:`waitcnt<amdgpu_synid7_waitcnt>`
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`param<amdgpu_synid7_param>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`attr<amdgpu_synid7_attr>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`, :ref:`attr<amdgpu_synid7_attr>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`, :ref:`attr<amdgpu_synid7_attr>`::ref:`b32<amdgpu_synid7_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_clrexcp
+ v_cos_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_1>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_exp_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_log_clamp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_log_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_log_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_mov_fed_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_movreld_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_movrels_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+ v_movrelsd_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rcp_clamp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rcp_clamp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rcp_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid7_sdst32_2>`, :ref:`vsrc<amdgpu_synid7_vsrc32_1>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_rsq_clamp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rsq_clamp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_rsq_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_0>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_add_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_addc_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
+ v_and_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_ashr_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`i32<amdgpu_synid7_type_dev>`
+ v_lshl_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_lshr_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mac_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mac_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_madak_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`imm32<amdgpu_synid7_fimm32>`
+ v_madmk_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`imm32<amdgpu_synid7_fimm32>`, :ref:`vsrc2<amdgpu_synid7_vsrc32_0>`
+ v_max_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_max_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_max_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_max_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_min_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_min_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_min_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_min_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_or_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid7_sdst32_2>`, :ref:`vsrc0<amdgpu_synid7_vsrc32_1>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_5>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_sub_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_subb_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
+ v_subbrev_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_subrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_2>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`ssrc0<amdgpu_synid7_ssrc32_6>`, :ref:`ssrc1<amdgpu_synid7_ssrc32_5>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_addc_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_ashr_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_ashr_i64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_bcnt_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_bfm_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_clrexcp_e64
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmps_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpsx_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_class_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmpx_class_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmpx_eq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_eq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_eq_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_eq_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_eq_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_eq_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_f_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_f_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_f_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_f_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_f_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_f_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_ge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_ge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_ge_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_ge_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_ge_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_ge_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_gt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_gt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_gt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_gt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_gt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_gt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_le_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_le_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_le_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_le_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_le_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_le_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_lg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_lg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_lt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_lt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_lt_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_lt_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_lt_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_lt_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_ne_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_ne_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_ne_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_ne_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_neq_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_neq_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nge_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nge_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_ngt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_ngt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nle_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nle_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nlg_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nlg_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nlt_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_nlt_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_o_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_o_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_t_i32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_t_i64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_t_u32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cmpx_t_u64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`
+ v_cmpx_tru_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_tru_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_u_f32_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cmpx_u_f64_e64 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_5>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cvt_pk_u16_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_cvt_pkaccum_u8_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_cvt_pknorm_i16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_pknorm_u16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src64_1>`, :ref:`src2<amdgpu_synid7_src64_1>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_log_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshl_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_lshr_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshr_b64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mac_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mac_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`i64<amdgpu_synid7_type_dev>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src64_1>`::ref:`u64<amdgpu_synid7_type_dev>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_max_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mbcnt_hi_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mbcnt_lo_u32_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_min_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_mov_fed_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_movrels_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+ v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b128<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`vsrc2<amdgpu_synid7_vsrc128_0>`::ref:`b128<amdgpu_synid7_type_dev>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_mullit_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_nop_e64
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+ v_rcp_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_clamp_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_clamp_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_clamp_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_legacy_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`src2<amdgpu_synid7_src32_4>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u8x4<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_subb_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_subbrev_u32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_4>`, :ref:`src1<amdgpu_synid7_src32_4>`, :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_i32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`src0<amdgpu_synid7_src32_4>`, :ref:`src1<amdgpu_synid7_src32_4>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`, :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid7_vdst64_0>`, :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgpu_synid7_src32_3>`, :ref:`src1<amdgpu_synid7_src32_4>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_eq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_eq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_f_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_f_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_ge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_ge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_gt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_gt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_le_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_le_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_lg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_lg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_lt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_lt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_neq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_neq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_nge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_nge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_ngt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_ngt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_nle_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_nle_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_nlg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_nlg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_nlt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_nlt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_o_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_o_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_tru_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_tru_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmps_u_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmps_u_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_eq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_eq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_f_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_f_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_ge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_ge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_gt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_gt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_le_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_le_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_lg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_lg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_lt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_lt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_neq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_neq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_nge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_nge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_ngt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_ngt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_nle_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_nle_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_nlg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_nlg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_nlt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_nlt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_o_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_o_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_tru_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_tru_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpsx_u_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpsx_u_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_class_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmpx_class_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`b32<amdgpu_synid7_type_dev>`
+ v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_f_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_f_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_f_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_f_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_f_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_f_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_le_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_le_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_le_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_le_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_le_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_le_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_o_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_o_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_t_i32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_t_i64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_t_u32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_t_u64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+ v_cmpx_u_f32 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+ v_cmpx_u_f64 :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src64_0>`, :ref:`vsrc1<amdgpu_synid7_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+ :hidden:
+
+ gfx7_attr
+ gfx7_bimm16
+ gfx7_bimm32
+ gfx7_fimm32
+ gfx7_hwreg
+ gfx7_label
+ gfx7_msg
+ gfx7_param
+ gfx7_simm16
+ gfx7_tgt
+ gfx7_uimm16
+ gfx7_waitcnt
+ gfx7_addr_buf
+ gfx7_addr_ds
+ gfx7_addr_flat
+ gfx7_addr_mimg
+ gfx7_base_smem_addr
+ gfx7_base_smem_buf
+ gfx7_data_buf_atomic128
+ gfx7_data_buf_atomic32
+ gfx7_data_buf_atomic64
+ gfx7_data_mimg_atomic_cmp
+ gfx7_data_mimg_atomic_reg
+ gfx7_data_mimg_store
+ gfx7_dst_buf_128
+ gfx7_dst_buf_64
+ gfx7_dst_buf_96
+ gfx7_dst_buf_lds
+ gfx7_dst_flat_atomic32
+ gfx7_dst_flat_atomic64
+ gfx7_dst_mimg_gather4
+ gfx7_dst_mimg_regular
+ gfx7_offset_buf
+ gfx7_offset_smem
+ gfx7_rsrc_buf
+ gfx7_rsrc_mimg
+ gfx7_samp_mimg
+ gfx7_sdst128_0
+ gfx7_sdst256_0
+ gfx7_sdst32_0
+ gfx7_sdst32_1
+ gfx7_sdst32_2
+ gfx7_sdst512_0
+ gfx7_sdst64_0
+ gfx7_sdst64_1
+ gfx7_src32_0
+ gfx7_src32_1
+ gfx7_src32_2
+ gfx7_src32_3
+ gfx7_src32_4
+ gfx7_src32_5
+ gfx7_src32_6
+ gfx7_src64_0
+ gfx7_src64_1
+ gfx7_src64_2
+ gfx7_src_exp
+ gfx7_ssrc32_0
+ gfx7_ssrc32_1
+ gfx7_ssrc32_2
+ gfx7_ssrc32_3
+ gfx7_ssrc32_4
+ gfx7_ssrc32_5
+ gfx7_ssrc32_6
+ gfx7_ssrc64_0
+ gfx7_ssrc64_1
+ gfx7_ssrc64_2
+ gfx7_ssrc64_3
+ gfx7_vcc_64
+ gfx7_vdata128_0
+ gfx7_vdata32_0
+ gfx7_vdata64_0
+ gfx7_vdata96_0
+ gfx7_vdst128_0
+ gfx7_vdst32_0
+ gfx7_vdst64_0
+ gfx7_vdst96_0
+ gfx7_vsrc128_0
+ gfx7_vsrc32_0
+ gfx7_vsrc32_1
+ gfx7_vsrc64_0
+ gfx7_mod
+ gfx7_opt
+ gfx7_ret
+ gfx7_type_dev
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