[PATCH] D67741: [MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:211
+  case AArch64::STGOffset:
+  case AArch64::STZGOffset:
+  case AArch64::ST2GOffset:
----------------
STZG and STZ2G store zero to the memory contents, so don't belong in this list according to the comment above. After reading the rest of the patch, I think it's the comment that's wrong, these instructions are allowed to write regular memory, but not with contents which depend on the address part of the input register.


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Comment at: llvm/test/CodeGen/AArch64/ldst-opt-mte.mir:4
+
+### STG and its offset limits
+
----------------
We should also test a mis-aligned offset (e.g. `$x0 = ADDXri $x0, 8, 0`) as well as the edges of the range.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67741/new/

https://reviews.llvm.org/D67741