[PATCH] D67596: AMDGPU/GlobalISel: Allow selection of scalar min/max
Alexander via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 18 23:48:21 PDT 2019
alex-t added a comment.
In D67596#1673947 <https://reviews.llvm.org/D67596#1673947>, @arsenm wrote:
> In D67596#1673887 <https://reviews.llvm.org/D67596#1673887>, @alex-t wrote:
>
> > I also have a question: why do you need to remove that predicates at all? Does it mean that to enable GlobalISel you'd need to remove all the divergent predicates stuff?
>
>
> The patterns are rejected for having custom predicate code. We don't need it as a standard pattern checks the register banks, which is what we really want. I think the cleanest compatibility solution would be to use divergence to guide register class selection, and somehow add the equivalent checks in the DAG patterns. Defining the equivalent GlobalISel pattern as always true would probably work, although leave a lot of clutter in the matching tables
Sounds good but I'd like to keep existing stuff working until we get ready to switch to the new solution.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67596/new/
https://reviews.llvm.org/D67596
More information about the llvm-commits
mailing list