[llvm] r372302 - [X86] Change a SmallVector& argument to SmallVectorImpl&. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed Sep 18 23:27:12 2019
New Revision: 372302

URL: http://llvm.org/viewvc/llvm-project?rev=372302&view=rev
Log:
[X86] Change a SmallVector& argument to SmallVectorImpl&. NFC

Avoids repeating the size.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=372302&r1=372301&r2=372302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 18 23:27:12 2019
@@ -2493,7 +2493,7 @@ static SDValue lowerMasksToReg(const SDV
 /// Breaks v64i1 value into two registers and adds the new node to the DAG
 static void Passv64i1ArgInRegs(
     const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
-    SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
+    SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA,
     CCValAssign &NextVA, const X86Subtarget &Subtarget) {
   assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
   assert(Subtarget.is32Bit() && "Expecting 32 bit target");