[llvm] r372298 - AMDGPU/SILoadStoreOptimizer: Add const to more functions
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 18 21:39:45 PDT 2019
Author: tstellar
Date: Wed Sep 18 21:39:45 2019
New Revision: 372298
URL: http://llvm.org/viewvc/llvm-project?rev=372298&view=rev
Log:
AMDGPU/SILoadStoreOptimizer: Add const to more functions
Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65901
Modified:
llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=372298&r1=372297&r2=372298&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp Wed Sep 18 21:39:45 2019
@@ -183,17 +183,17 @@ private:
MachineBasicBlock::iterator mergeBufferStorePair(CombineInfo &CI);
void updateBaseAndOffset(MachineInstr &I, unsigned NewBase,
- int32_t NewOffset);
- unsigned computeBase(MachineInstr &MI, const MemAddress &Addr);
- MachineOperand createRegOrImm(int32_t Val, MachineInstr &MI);
- Optional<int32_t> extractConstOffset(const MachineOperand &Op);
- void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr);
+ int32_t NewOffset) const;
+ unsigned computeBase(MachineInstr &MI, const MemAddress &Addr) const;
+ MachineOperand createRegOrImm(int32_t Val, MachineInstr &MI) const;
+ Optional<int32_t> extractConstOffset(const MachineOperand &Op) const;
+ void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr) const;
/// Promotes constant offset to the immediate by adjusting the base. It
/// tries to use a base from the nearby instructions that allows it to have
/// a 13bit constant offset which gets promoted to the immediate.
bool promoteConstantOffsetToImm(MachineInstr &CI,
MemInfoMap &Visited,
- SmallPtrSet<MachineInstr *, 4> &Promoted);
+ SmallPtrSet<MachineInstr *, 4> &Promoted) const;
public:
static char ID;
@@ -1151,7 +1151,7 @@ SILoadStoreOptimizer::mergeBufferStorePa
}
MachineOperand
-SILoadStoreOptimizer::createRegOrImm(int32_t Val, MachineInstr &MI) {
+SILoadStoreOptimizer::createRegOrImm(int32_t Val, MachineInstr &MI) const {
APInt V(32, Val, true);
if (TII->isInlineConstant(V))
return MachineOperand::CreateImm(Val);
@@ -1168,7 +1168,7 @@ SILoadStoreOptimizer::createRegOrImm(int
// Compute base address using Addr and return the final register.
unsigned SILoadStoreOptimizer::computeBase(MachineInstr &MI,
- const MemAddress &Addr) {
+ const MemAddress &Addr) const {
MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::iterator MBBI = MI.getIterator();
DebugLoc DL = MI.getDebugLoc();
@@ -1227,13 +1227,13 @@ unsigned SILoadStoreOptimizer::computeBa
// Update base and offset with the NewBase and NewOffset in MI.
void SILoadStoreOptimizer::updateBaseAndOffset(MachineInstr &MI,
unsigned NewBase,
- int32_t NewOffset) {
+ int32_t NewOffset) const {
TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase);
TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset);
}
Optional<int32_t>
-SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) {
+SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
if (Op.isImm())
return Op.getImm();
@@ -1259,7 +1259,7 @@ SILoadStoreOptimizer::extractConstOffset
// %Base:vreg_64 =
// REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1
void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base,
- MemAddress &Addr) {
+ MemAddress &Addr) const {
if (!Base.isReg())
return;
@@ -1314,7 +1314,7 @@ void SILoadStoreOptimizer::processBaseWi
bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
MachineInstr &MI,
MemInfoMap &Visited,
- SmallPtrSet<MachineInstr *, 4> &AnchorList) {
+ SmallPtrSet<MachineInstr *, 4> &AnchorList) const {
if (!(MI.mayLoad() ^ MI.mayStore()))
return false;
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