[PATCH] D66805: [MIPS] For vectors, select `add %x, C` as `sub %x, -C` if it results in inline immediate

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 18 12:59:43 PDT 2019


lebedev.ri marked an inline comment as done.
lebedev.ri added inline comments.


================
Comment at: llvm/test/CodeGen/Mips/msa/arithmetic.ll:220-241
 define void @sub_v2i64_i(<2 x i64>* %c, <2 x i64>* %a) nounwind {
 ; MIPS-LABEL: sub_v2i64_i:
 ; MIPS:       # %bb.0:
 ; MIPS-NEXT:    ldi.b $w0, -1
 ; MIPS-NEXT:    shf.w $w0, $w0, 177
 ; MIPS-NEXT:    ld.d $w1, 0($5)
 ; MIPS-NEXT:    addv.d $w0, $w1, $w0
----------------
atanasyan wrote:
> lebedev.ri wrote:
> > Hm, this one didn't get recovered by the patch.
> I saw this regression. Unfortunately I could not quickly create a fix for it. As far as I remember, the problem is in this statement `auto *BVN = dyn_cast<BuildVectorSDNode>(C)`. In `@sub_v2i64_i` the second operand (i.e. `C`) is a bitcast and `dyn_cast<BuildVectorSDNode>` returns zero. Right now I do not have a time to dig it. Maybe next week.
Honestly i didn't notice that it didn't address all of the patterns until now.
We get:
```
t10: v2i64 = add t7, t16
  t7: v2i64,ch = load<(load 16 from %ir.a)> t0, t4, undef:i32
    t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t3: i32 = Register %1
    t6: i32 = undef
  t16: v2i64 = bitcast t15
    t15: v4i32 = BUILD_VECTOR Constant:i32<-1>, Constant:i32<-31>, Constant:i32<-1>, Constant:i32<-31>
      t14: i32 = Constant<-1>
      t13: i32 = Constant<-31>
      t14: i32 = Constant<-1>
      t13: i32 = Constant<-31>
```
So yes, this because of a bitcast.
Even if we look past it, `isConstantSplat()` will say "no, not a splat".
This likely means something else other than `isConstantSplat()` should be used here.


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